制度:新 ; 報告番号:甲3602号 ; 学位の種類:博士(工学) ; 授与年月日:2012/3/15 ; 早大学位記番号:新595

He Xun

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早稲田大学大学院情報生産システム研究科     博 士 論 文 概 要         論  文  題  目             申  請  者 HE, Xun  情報生産システム工学専攻 マルチメディアシステム研究       2012 年 2 月  SIMD Based Multicore Processor for Image and Video Processing    2 Cont inuous  i mprove men t s  in  image  and  v ideo  p rocess ing  r equ i r e  h igh  computa t iona l  power  to  dea l  wi th  the  inc reas ing  complex i ty  o f  a lgo r i thms  and  h ighe r  de f in i t ion  v ideo .  Meanwhi l e ,  deve lopmen t  in  VLSI  t echno logy  a l lows  the  in t eg ra t ion  o f  more  co res  on  a  s ing le  ch ip  fo r  ach iev ing  h ighe r  pe r fo r mance .  The re  a re  t h ree  l eve l s  o f  pa ra l l e l i sm in  app l i ca t ions :  t a sk  l eve l ,  da t a  l eve l  and  ins t ruc t ion  l eve l .  Typ ica l ly,  mu l t i core  a r ch i t ec tu re  can  ob ta in  h igh  t a sk  l eve l  pa ra l l e l i sm,  SIMD can  ach ieve  h igh  da t a  l eve l  pa ra l l e l i sm,  and  VLIW a rch i t ec tu re  can  ach i eve  h igh  ins t ruc t ion  l eve l  pa ra l l e l i sm.  However,  ha rdware  cos t s  and  pe r fo rmance  ga ins  o f  t he  th ree  me thods  a re  qu i t e  d i ff e ren t  fo r  v ideo  p rocess ing .  Mul t i co re  can  ach ieve  a lmos t  doub le  pe r fo r mance  ga ins  wi th  doub le  ha rdware  cos t s  fo r  a  v ideo  encoder.  S IMD can  ach ieve  doub le  da ta  l eve l  pa ra l l e l i sm wi th  l e s s  t han  doub le  ga t e s .  VLIW needs  more  than  doub le  ga te s  fo r  doub le  in s t ruc t ion  l eve l  pa ra l l e l i sm.  Ba sed  on  these  t echno log ies ,  we  des ign  and  fab r i ca t e  a  32  core s  p roces sor,  and  a l so  eva lua te  i t s  pe r fo rmance .  The  r e su l t s  show tha t  t h i s  p rocesso r  can  ach i eve  ve ry  h igh  pe r fo r mance  fo r  our  t a rge t  app l i ca t ions .    Chapter 1  [ Introduct ion]  p re sen t s  a  background  in t roduc t ion  o f  pa ra l l e l  a r ch i t ec tu res  and  cha l l enges  i n  mul t i co re  p roces sor.  Chapter 2  [SIMD based  Core  Arch i tec ture]  p r esen t s  t he  S IMD based  co re  a rch i t ec tu re .  Fo r  max imiz ing  on-ch ip  pa ra l l e l i sm,  mul t i co re  and  128  b i t s  S IMD a rch i t ec tu re  i s  app l i ed .  S IMD ins t ruc t ion  se t  i s  op t imized  fo r  mul t i med ia  app l i ca t ions .  The  co re  i s  cons i s t ed  by  one  sma l l  32  b i t s  RISC core ,  and  SIMD p ipe l ines .  RISC i s  based  on  open  source  p ro jec t :  OR1200 .  SIMD i s  d iv ided  in to  two  pa r t s  fo r  execu t ing  two  ins t ruc t ions  a t  t he  same  3 t ime .  Compar ing  wi th  CELL p rocesso r ’s  S IMD,  the  p roposed  work  can  r educe  by  29% cyc le  coun t  fo r  v ideo  app l i ca t ions .  Chapter 3  [Appl i ca t ion  Spec i f i ed  Cache  Coherence  Protoco l ]  p roposes  a  manua l ly  con t ro l l ed  inva l id  cache  cohe rence  p ro toco l  (MCI) .  In  mul t i co r e  sys t em,  t he  cache  cohe rence  p rob lem becomes  more  and  more  impor t an t  w i th  co re  number.  In  conven t iona l  snoop ing  based  p ro toco l ,  cohe rence  t r ansac t ion  b roadcas t s  t o  a l l  cache  moni to r s .  M.  Ekman’s  Exper imen t s  in  WDDD2002  show tha t  more  than  70% pe rcen tage  o f  a l l  snoop ing  ope ra t ions  mi s ses  in  o the r  caches  fo r  conven t iona l  MOESI  p ro toco l .  Th i s  means  tha t  mos t  o f  the  snoop ing  induced  t ag - lookups  ju s t  was te  the  power.  In  the  p roposed  MCI  p ro toco l ,  me mory  space  can  be  dyna mica l ly  o r  s t a t i ca l l y  de f ined  as  sha red  o r  p r iva t e  space .  The  sha red  spaces  can  be  sha red  by  a l l  co res ,  c lus t e r s  o r  s eve ra l  co res .  A new p rog ramming  mode l  i s  p roposed  fo r  de f in ing  the  sha r ing  pa t t e rns .  A snooping  un i t  i s  added  fo r  each  core ,  wh ich  keeps  the  sha r ing  conf igu ra t ions  and  sends  ou t  i nva l id  messages  au tomat i ca l ly.  Fo r  MCI ,  t he  cos t  fo r  cohe rence  i s  ma in ly  de te rmined  by  da ta  sha r ing  me thod ,  no t  t he  number  o f  co res .  La rge  sca l e  SMP processor  can  a l so  ach i eve  good  pe r fo r mance  in  MCI .  In  our  expe r iment s ,  MCI  i s  compared  wi th  Je t ty  wh ich  i s  p roposed  fo r  r educed  snoop ing  ope ra t ions  by  A .  Moshovos  in  HPCA2001 .  For  a  32 -co re  p rocessor,  snoop ing  ope ra t ions  o f  MOESI  p ro toco l  cos t s  more  than  50% of  L1  cache ’s  power.  J e t ty  can  r educe  abou t  24 .6% snoop ing  ope ra t ions  fo r  MOESI .  Snoop ing  ope ra t i ons  in  the  p roposed  MCI  p ro toco l  i s  abou t  42 .7% le s s  than  MOSEI  wi th  Je t ty.    Chapter 4  [Communicat ion  Net work]  desc r ibes  a  Core  In t e rconnec t ion  Bus  (CIB)  fo r  connec t ing  e igh t  cores .  In  t h i s  p rocessor,  t he re  a r e  fou r  4 c lus t e r s ,  and  each  c lus t e r  i s  cons i s t ed  by  8  co res  and  one  sha red  cache .  Da ta  sha r ing  wi th in  c lus t e r  i s  suppor t ed  by  the  sha r ing  cache .  However,  i t ’s  i ne ff i c i en t  t o  use  the  sha red  cache  fo r  da ta  communica t ion  be tween  SIM D cores ,  a s  i t  needs  a  wr i t e  back  and  r ead  ope ra t ion  to  L2 .To  enhance  the  da t a  co mmunica t ion  ab i l i t y  fo r  S IMD core ,  CIB  i s  des igned  fo r  ach iev ing  ve ry  low l a t ency  da t a  t r ans fe r  be tween  cores .  Vec to r  cores  d i r ec t ly  exchange  da ta  th rough  CIB.  In  CIB ,  eve ry  f l i t  has  rou t ing  heade r,  and  they  sha re  the  l i nks  in  t ime-d iv i s ion  mul t ip l ex ing  me thod .  Da ta  t r ansmiss ions  a re  d iv ided  in to  independen t  f l i t s .  Each  f l i t  can  rou te  in  CIB  independen t ly.  CIB  can  b roadcas t  one  f l i t  t o  a l l  co res ,  which  i s  no t  suppor t ed  in  channe l  based  NoC.  Compar ing  wi th  S .  R .  Vanga l ’s  NoC des ign  in  JSSC08 ,  CIB  doesn ’ t  s to re  da ta  f l i t s ,  which  can  save  a  lo t  o f  bu ffe r  r e sources .  Thus  CIB can  ach i eve  more  than  10  GB/s  BW fo r  sma l l  s i ze  vec to r  t r ans fe r s ,  wh ich  i s  more  than  2 .5  t imes  be t t e r  t han  S .  R .  Vanga l ’s  work .  When  the  i n j ec t ion  r a t e  i s  l e s s  t han  8% ,  CIB’s  l a t ency  i s  l e s s  t han  4  cyc l e s  i n  average .   Chapter 5  [Chip  implementat ion  and  Per formance  Evaluat ion]  shows  the  ch ip  imp lementa t ion  and  pe r fo rma nce  eva lua t ion  o f  the  p roposed  32  co res  p rocesso r.  App ly ing  the  p roposed  t echno logy  toge the r,  a  32  co res  p rocesso r  has  been  f abr i ca t ed  and  ve r i f i ed  in  SMIC 65  nm CMOS.  Th i s  ch ip  i s  cons i s t ed  by  32  co res  (286KGates  pe r  co re ) ,  256KB L2  cache ,  two  PLL,  and  one  64-b i t  DDR PHY,  and  the  d i e  i s  abou t  25  mm2.Th i s  p rocesso r  can  ach i eve  a  max i mum speed  o f  750  MHz a t  1 .2  V co re  power.  The  who le  ch ip  can  ach ieve  a  peak  pe r fo rmance  o f  375  GMACs ,  o r  750  GOPS o f  8 -b i t  da ta  ope ra t ions .  I t  can  ach ieve  1 .9  t imes  h ighe r  GMACs  pe r fo r mance  than  D.  N .  Truong’s  167  RISC cores  ch ip  in  JSSC09 .  For  SAD (Sum of  Abso lu te  Di ff e rence )  and  5 Matr ix  Mul t ip ly  ke rne l s ,  t he  p roposed  work’s  cyc le  coun t  i s  r educed  by  37% than  TI  C6415  DSP.   Chapter 6  [Extended Processor wi th  Hardware  Acce lerator]  p re sen t s  a  sha r ing  ha rdware  acce le ra to r  fo r  ex tend ing  the  p roposed  SIMD processo r.  Th i s  mul t i co re  p l a t fo rm i s  des igned  fo r  h igh  pe r fo rmance  mul t ime dia  app l i ca t ions  by  max i miz ing  on-ch ip  da t a  l eve l  and  t a sk  l eve l  pa ra l l e l i sm.  However,  t he re  a r e  l imi t a t ions  fo r  h igh  pa ra l l e l  sys t em:  sequen t i a l  func t ions  wi th  l e s s  pa ra l l e l i sm become  the  bo t t leneck .  Hardware  acce l e ra to r s  a r e  added  fo r  r e so lv ing  these  p rob lems .  As  the  usage  ra t e  o f  acce l e ra to r s  i s  ve ry  low,  i t ’s  unnecessa ry  to  add  the  sa me  acce l e ra to r  fo r  eve ry  core  o f  mul t i core  p rocesso r.  Sha r ing  r e sources  and  r educ ing  the  cos t  becomes  a  ho t  t op i c  r ecen t ly  fo r  mul t i co re  p rocesso r.  The  low l a t ency  CIB ne twork  makes  i t  pos s ib l e  fo r  sha r ing  ha rdware  acce l e ra to r s  w i th in  a  c lus t e r.  Based  on  our  p rev ious  works  on  4Kx2K@60fps  H .264  Decoder,  an  in t r a  decode r  i s  added  in  the  mul t i co re  p l a t fo r m as  a  sha red  ha rdware  acce le ra to r.  I t  can  sa t i s fy  e igh t  channe l s  pa ra l l e l  HD decod ing  a t  31  MHz.   Chapter 7  [Conc lus ion]  summar ie s  the  p roposa l s .  Based  on  th i s  des ign ,  t he  p roposed  32-co re  SIMD processo r  can  be  app l i ed  fo r  a  lo t  o f  mu l t ime dia  app l i ca t i ons ,  such  a s  v ideo  decod ing  o r  image  p rocess ing .  The  dua l - i s sue  SIMD cores  can  gua ran tee  ve ry  h igh  pe r fo r mance  fo r  p rocess ing  8 -b i t  p ixe l s .  Toge the r  wi th  ha rdware  acce le r a to r s ,  t he  app l i ca t ion  f i e lds  can  be  wide r.     

SIMD based multicore processor for image and video processing

制度:新 ; 報告番号:甲3602号 ; 学位の種類:博士(工学) ; 授与年月日:2012/3/15 ; 早大学位記番号:新5956textthesi

He, Xun

32447

Waseda University Repository

https://waseda.repo.nii.ac.jp/?action=repository_action_common_download&item_id=19566&item_no=1&attribute_id=20&file_no=3

SIMD based multicore processor for image and video processing

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