A Compact Analytical Design of Dual-Loop 18 GHz Frequency Synthesizer to Enhance Signal Reliability in Digital Millimeter Radio Link System

In this paper a high resolution dual-loop 17.7�19.7 GHz frequency synthesizer is presented which is compatible with ITU-R (F.595-6) standards. The investigations of phase noise and spur frequency contents are discussed in detail. The simulated and measured phase noise and spur frequency contents are similar to one another. Phase noise of �81 dBc/Hz in 17.7 GHz at 10 KHz offset frequency is measured by (HP8560) series Spectrum analyzer and it matches with predicted measurements. This record was migrated from the OpenDepot repository service in June, 2017 before shutting down

Clock And Data Recovery Using Bang-bang Pll’s

Tez (Yüksek Lisans) -- İstanbul Teknik Üniversitesi, Fen Bilimleri Enstitüsü, 2008Thesis (M.Sc.) -- İstanbul Technical University, Institute of Science and Technology, 2008Bu çalışmada, saat ve data işaretlerinin yeniden çıkarımında kullanılan iki konumlu faz kititlemeli çevrimlerden bahsedilmiştir. Sistem seviyesinde hızlı simülasyonlar yapabilmek amacıyla çevrim elemanlarının davranışsal modelleri geliştirilmiştir. İki konumlu kontrol sistemlerinin el ile analizinin oldukça zor olmasından dolayı modelleme zorunlu hale gelmektedir. Ayrıca gerçeklenen elemanların idealsizliklerinden kaynaklanan davranışlar da olabilidiğince modellenmeye çalışılmıştır. Söz konusu faz kilitlemeli çevrimlerin sistem seviyesinde sağlaması gereken özelliklerin kabaca hesaplanması ve datadaki değişim sıklığının bu özellikleri nasıl etkilediği anlatılmıştır. Çevrim elemanlarının tranzistör seviyesinde nasıl gerçeklendiklerinden bahsedilmiştir. Çok kullanılan bir ring osilatör yapısı olan simetrik yüklü osilatör (Maneatis yük) çevrimde etkili bir şekilde kullanabilmek amacıyla modifiye edilmiştir. Osilatörün üretim ve sıcaklık değişimlerini tolere edebilmesi için kazancının yüksek olması gerekir. Bu da sistemin harici gürültü kaynaklarına (besleme, taban gürültüsü gibi) olan duyarlılığını oldukça arttırmaktadır. Bu nedenle osilatörü otomatik olarak kalibre eden bir teknik geliştirilmiştir. Değişik faz kilitlemeli çevrimlere uygulanabilen teknik için osilatörün akım kontollü olması gerekmektedir. Frekans kitlenmesi gerçekleştikten sonra osilatörün akımı bir analog-sayısal çevirici ile örneklenmekte ve asıl sistem bu nokta etrafında daha dar bir bölgede çalışmaktadır. Ayrıca, sıcaklıktan kaynaklanabilecek değişimler de analog-sayısal dönüştürücünün refererans akımı üzerinden kompanze edilmektedir. Son olarak, tasarlanan sistemin simülasyon sonuçları verilmiştir. 0.18um CMOS teknolojisinde tasarlanan devre 5Gb/s data hızlarında çalışabilmektedir.In this work, bang-bang PLL structures, which are extensively used in clock and data recovery systems, are investigated. Behavioral models of loop elements are created to do faster simulations in system level. This step is mandatory in bang-bang systems, which are hard to analyze with simple calculations. Some non-idealities of real circuit elements are inserted to these models. System level design issues of bang-bang PLL’s are discussed and the effect of data transition density to system specifications is mentioned. Transistor level implementations of loop elements are described. A popular delay cell with symmetric loads (Maneatis cell) is modified to be used effectively in a bang-bang loop. Gain of the VCO seems very large after initial design, which is required to cover the operating frequency range over process and temperature corners. Large gain makes the system prone to external noise sources such as noise from power supply, substrate etc. Therefore, an automatic calibration method is developed to reduce the VCO gain. This technique can be applied to any current controlled oscillators in various phase locked loops. After frequency lock is achieved, current of the oscillator is sampled by a current mode ADC and a narrower range is generated around that point. Additionally, frequency variation due to temperature is compensated through the specifically designed reference current of ADC. Finally, simulation results of CDR and calibration circuits are given. CDR is designed in 0.18um CMOS technology and can operate at 5Gb/s data rate.Yüksek LisansM.Sc

A PLL Design Based on a Standing Wave Resonant Oscillator

In this thesis, we present a new continuously variable high frequency standing wave oscillator and demonstrate its use in generating the phase locked clock signal of a digital IC. The ring based standing wave resonant oscillator is implemented with a plurality of wires connected in a mobius configuration, with a cross coupled inverter pair connected across the wires. The oscillation frequency can be modulated by coarse and fine tuning. Coarse modification is achieved by altering the number of wires in the ring that participate in the oscillation, by driving a digital word to a set of passgates which are connected to each wire in the ring. Fine tuning of the oscillation frequency is achieved by varying the body bias voltage of both the PMOS transistors in the cross coupled inverter pair which sustains the oscillations in the resonant ring. We validated our PLL design in a 90nm process technology. 3D parasitic RLCs for our oscillator ring were extracted with skin effect accounted for. Our PLL provides a frequency locking range from 6 GHz to 9 GHz, with a center frequency of 7.5 GHz. The oscillator alone consumes about 25 mW of power, and the complete PLL consumes a power of 28.5 mW. The observed jitter of the PLL is 2.56 percent. These numbers are significant improvements over the prior art in standing wave based PLLs

High frequency and high performance voltage controlled oscillator for wireless communications

制度:新 ; 文部省報告番号:甲2632号 ; 学位の種類:博士(工学) ; 授与年月日:2008/3/15 ; 早大学位記番号:新479

Ultra-low-energy transmitters for battery-free wireless sensor networks

As the number of autonomous data collection applications keep increasing, the demand for wireless sensor networks (WSNs) has seen explosive growth. In this dissertation, an ultra-low-energy WSN transmitter is developed to reduce the energy consumption of sensor nodes in WSNs. With an ultra-low-energy transceiver, it is possible to eliminate the battery in the sensor node and power itself with an energy harvester, thus creating a battery-free sensor node. A variety of applications can be accommodated with the battery-free sensor node as it has small size, light weight, and endless lifetime. Two prototype WSN transmitters are implemented to demonstrate the transmitter energy minimization. The first transmitter incorporates a fast frequency calibration to shorten the oscillation frequency tuning time. This minimizes energy wasted during the transmitter start-up period. The energy consumption of the second transmitter that employs a power oscillator architecture is minimized by maximizing the transmitter efficiency. The efficiency of the power oscillator circuit is analyzed and the design procedure for maximum efficiency is then developed. Prototype WSN transmitters were fabricated in 0.18-um CMOS technology. The first transmitter operates in the 915-MHz ISM band. With 0.5-MHz reference frequency, the transmitter takes only 72 us for the BFSK frequency calibration. It dissipates a power of 1.91 mW while radiating a power of -2.9 dBm. The second transmitter operates in the 2.45-GHz ISM band on a single supply of 0.65 V. The transmitter has efficiency as high as 23 % at -5.2 dBm radiated power. This corresponds to a low power consumption of 1.34 mW

LOW-POWER FREQUENCY SYNTHESIS BASED ON INJECTION LOCKING

Ph.DDOCTOR OF PHILOSOPH