In this paper a high resolution dual-loop 17.7�19.7 GHz frequency synthesizer is presented which is compatible with ITU-R (F.595-6) standards. The investigations of phase noise and spur frequency contents are discussed in detail. The simulated and measured phase noise and spur frequency contents are similar to one another. Phase noise of �81 dBc/Hz in 17.7 GHz at 10 KHz offset frequency is measured by (HP8560) series Spectrum analyzer and it matches with predicted measurements. This record was migrated from the OpenDepot repository service in June, 2017 before shutting down

Ameri Mahabadi, Hossein

Attaran, A.

Moghavvemi, M.

English

ZENODO

Frequenz, Vol. 65 (2011), pp. 29–35 Copyright © 2011 De Gruyter. DOI 10.1515/FREQ.2011.005A Compact Analytical Design of Dual-Loop 18GHz FrequencySynthesizer to Enhance Signal Reliability in Digital MillimeterRadio Link SystemMahmoud Moghavvemi,1; Hossein Ameri1 andAliyar Attaran11 University of Malaya, MalaysiaAbstract. In this paper a high resolution dual-loop 17.7–19.7 GHz frequency synthesizer is presented which is com-patible with ITU-R (F.595-6) standards. The investigationsof phase noise and spur frequency contents are discussed indetail. The simulated and measured phase noise and spurfrequency contents are similar to one another. Phase noiseof  81 dBc/Hz in 17.7 GHz at 10 KHz offset frequencyis measured by (HP8560) series Spectrum analyzer and itmatches with predicted measurements.Keywords. Dual-Band, Frequency Synthesizer,IRTU-R (F.595-6), Digital Millimeter Radio Link System.PACS®(2010). 06.30.Ft, 06.20.fb, 84.40.-x, 07.57.Kp,07.57.Hm.1 IntroductionA high frequency dual-loop frequency synthesizer is verycomplex to construct but it is a crucial functional blockin telecommunication systems. It has the least trade-offsamong all synthesizer structures. In a dual-loop frequencysynthesis structure, one synthesizer loop operates in highfrequency and consumes more power than other loops.In wireless transmission systems, synthesizers are theheart of the system in which data transmission perfor-mances such as channel speed switching, signal purity andintegrity are determined. Indirect synthesis such as dual-loop structure can offer these performance requirementsunlike direct-digital synthesis (DDS) where the modulatedsignal is directly synthesized at the output frequency withadequate performance quality ([1–3]). The high resolutionCorresponding author: Mahmoud Moghavvemi, Center ofResearch in Applied Electronics CRAE, Department of Engineering,University of Malaya, 50603 Malaysia;E-mail: mahmoud@um.edu.my.Received: October 29, 2010.property allows not only a fine channel frequency selection,but accurate constant-amplitude continuous-phase modula-tion at the output frequency ([4]).Figure 1 illustrates a general synthesizer block diagram.The relationship between input reference frequency andoutput frequency is shown by equation (1):Foutput D MRFr : (1)The relationship between the output phase noise and refer-ence frequency phase noise is as below:PNoutput D PNr C20 log MR: (2)For achieving an acceptable phase noise with good reso-lution, a dual-loop synthesizer structure is introduced, inwhich one loop generates low frequency with low step size,and the other loop generates high frequency with large stepsize. By mixing the output frequency of these two loops, ahigh frequency with low step size can be achieved.A general dual-loop synthesizer block diagram is shownin Figure 2.The output frequency equation is given by equation (3):Fout D M1R1Fr1 C M2R2Fr2: (3)For dual-loop synthesizers working in Ku band, one singleloop in L band and one single loop in X-band are designedto achieve 18 GHz output.The modeled phase noise contributed from each func-tional synthesizer loop block is shown in Figure 3.Table 1 shows an extensive performance comparison be-tween various synthesizer structures based on their perfor-mance.2 Phase Noise ModelingPhase noise dictates the performance quality of the high-speed telecommunication transceivers. Phase noise infrequency-domain and jitter noise in time-domain are usedto characterize digital micrometer wave link systems forhigh-speed radio application.Brought to you by | University of Malaya Medical Library (University of Malaya Medical Library)Authenticated | 172.16.1.226Download Date | 7/27/12 6:53 AM30 M. Moghavvemi, H. Ameri and A. AttaranFigure 1. Basic single loop block diagram of a synthesizer.In Figure 1, the third order loop filter, trans-impedancecan be expressed as:G .s/ D Zi .f / 1i2f C3Zi .f /CR3 C 1i2f C3; (4)G .s/ D i2fR2C2 C 1i2f  .i2fR2C2C1 C C1 C C2/ : (5)Generally, every functional loop block in the synthesizer isa noise source (intrinsic). All the intrinsic noise sourcesin the synthesizer loop are uncorrelated. Hence the power-spectrum density (PSD) noise at the output is the superpo-sition of all the noise contributions from each block multi-plied by their noise transfer function ([5]).Reference noise Nref is the phase noise contribution ofreference oscillator in .f / offset frequency, and it can bemodeled as:Nref .f / D Nref .f / .f /2f 2CNref-floor (6)where Nref .f / is the phase noise at f offset frequencyin the  20 dB/dec spectrum region, Nref-floor is the noisefloor of the reference oscillator.The noise from the reference oscillator in the output willbeNref;inoutput D NrefN 2H 2where H D 1   11C H0N: (7)Phase detector noise NPDF-ref is generated in transistor-level integrated-circuitry (IC) fabricated in factory, whosenoise floor is proportional to 10 log.Fref=1 Hz/. The actualnoise is flat with respect to the operating frequency, and bysetting a proper loop bandwidth, the effective NPFD can befiltered out ([6]).log .NPFD/ D Gcl .f / NPDF-ref C 10 log. Fref1 Hz /20(8)where Gcl .f / is the close-loop gain of the synthesizer loop([8]).Loop filter noise Nfil can be modeled from noise currentand the admittance of the loop filter, Yfil.Nfil .s/ D 2 K  T Re.Yfil .s// (9)whereK is Boltzmann’s constant, T is the absolute temper-ature, and Yfil is 1=Zi C 1=Zo, as shown in Figure 2, thecomplex admittance of the loop filter. Finally the loop filtercontribution in output can be expressed as ([7, 8])Nfil;inoutput D Nfil .s/ jG .s/j2ˇˇˇKVCOsˇˇˇ2  .1  H 2/ (10)Charge-pump noiseNCP exhibits flicker noise (1=f / andthermal noise, which is proportional to the duty cycle ˛CP.For a large ˛CP, the flicker noise corner will be high and thegenerated thermal noise will be small compared to flickernoise ([8]).NCP;inoutput D NCP  jG.s/j2 ˇˇˇKVCOsˇˇˇ2  .1  H 2/: (11)VCO noise NVCO can be modeled asNVCO .f / D NVCO .f / .f /2f 21C fc;VCOfCNVCO;floor (12)where NVCO .f / is the VCO phase noise at f offsetfrequency, fc;VCO is the 1=f 3 noise corner of VCO andNVCO;floor is the noise floor of VCO. The VCO noise contri-bution in the output frequency can be expressed as ([6])NVCO;inoutput D NVCO j1  H j2 : (13)For uncorrelated noise sources, the respective noise spectramust be summed up to obtain total phase noise spectrum atthe frequency synthesizer output.Ntotal;inoutput D Nref;inoutput CNPFD;inoutputCNCP;inoutput CN fil;inoutputCNVCO;inoutput CNdivider;inoutput:The modeled phase noise contributed from each functionalsynthesizer loop block is shown in Figure 3.Table 1 shows an extensive performance comparison be-tween various synthesizer structures based on their perfor-mance.Brought to you by | University of Malaya Medical Library (University of Malaya Medical Library)Authenticated | 172.16.1.226Download Date | 7/27/12 6:53 AMA Compact Analytical Design of Dual-Loop 18 GHz Frequency Synthesizer 31Figure 2. Basic block diagram of dual-loop synthesizer.3 System Block DiagramThe block diagram of the 18 GHz synthesizer is shown inFigure 4. The structure is dual loop and thus there are twophase lock loops to generate the IF and LO signals. Bothsignals are combined in a sub harmonic mixer, generatingthe desired output frequency.In the IF PLL, a TCXO10 is used as the reference of10 MHz half sinewave signal. The used crystal’s high phasenoise performance (Table 3) and high slope in the loweredge of the signal are the main advantages of this chipwhich improves the phase detector efficiency.For the phase detection part, a chip is selected that in-cludes a phase/frequency detector and two internal digitalfrequency dividers M and R. The M and R values are de-termined by a programmable microcontroller and applied tothe phase detector.An MMIC is used as the VCO. This MMIC operates at5 v, 10 mA DC bias. The output signal frequency of theVCO is in the 970–2150 MHz range and has a good phasenoise as indicated in Table 2. The VCO’s output signal issampled and used as a feedback to PD.In the fabricated synthesizer, the R and M values areprogrammed to be 5 and 518, respectively. The resultingFigure 3. Modeled phase noise spectrum using theformulas.output frequency signal fIF in the locked loop state is equaltofIF D MRfr H) fIF D 1036 MHz : (14)The IF signals is passed through an amplifier to have an ac-ceptable power level at the mixer input. The schematic ofBrought to you by | University of Malaya Medical Library (University of Malaya Medical Library)Authenticated | 172.16.1.226Download Date | 7/27/12 6:53 AM32 M. Moghavvemi, H. Ameri and A. AttaranFigure 4. The 18 GHz synthesizer block diagram. 1 2 3 4ABCD4321DCBA TitleNumber RevisionSizeBDate: 10-Nov-2007 Sheet    of File: H:\sotoodeh\sy nthesizer papers\sy nth_18.ddb Drawn By :C17R9R7R10R6C16C20R1C6C67C21 C62R8C15R5C8R11R12C14C3 C4C5++++-Cext13S_Data4S_Clk5S_WR3LD14Dout15PD_D17PD_U18VDD1VDD9VDD16GND6GND12GND19Fin10Fin-11Fr20U2AC2C9C22+C1S-DATS-CLKS-WRS-LD1423coup1N/C6N/C5N/C4N/C3N/C2N/C1N/C7N/C8N/C9N/C10N/C11N/C12N/C24N/C23VTUNE222121VCC20N/C19N/C18N/C17RF OUT16GND15N/C14N/C13GND25U4R4R15R2R3C13R18R17R16C52C10C11 C12C65IN5N/C6IN7GND8OUT1NC2OUT3VCC4GND9U5C60R5014dBmL1L2L5C667GND8out241356U1VCC1VCC2VCC2LOVCC2VCC3VCC46-2+34718U3Figure 5. The IF PLL circuit schematic.Brought to you by | University of Malaya Medical Library (University of Malaya Medical Library)Authenticated | 172.16.1.226Download Date | 7/27/12 6:53 AMA Compact Analytical Design of Dual-Loop 18 GHz Frequency Synthesizer 33Refer-enceFrequencyrange(GHz)Structure Technology Tuning(%)Phase noise(dBc/Hz)Supplyvoltage(V)Spurscontent(dBc)Gainpower[9] 24 2 step up-conversion mixer0.18umCMOS5 — 2.5 — 26.5 dBm[10] 13.9–15.6Integer-N 0.18umCMOS12.2  103.8 @1 MHz1.8 — 60 dBc[11] 2–18 MMIC 0.2umPHEMT88  80 @100 KHz— < 55 —[12] 17 Integer-N,QVCO0.18umCMOS16.5  110 @1 MHz1 — —[13] 6.3–9 Integer-N 0.18umCMOS30  109 @1 MHz1.8  52 —[14] 10 Integer-N 0.18umCMOS—  102 @1 MHz1.8  48 —[15] 22–29 Direct-conversion0.18umSiGe BiC-MOS24  100.4 @1 MHz1.8  47 35/31 dB[16] 24.2 Integer-N 0.18umCMOS6  106 @100 KHz1 — —[17] 3.1–8 Integer-N, mixer 0.18umCMOS158  126 @10 MHz1.8 — 81.5–85.2 dB[18] 16–18.8 Integer-N 0.13umSiGe BiC-MOS14.89  90 @100 KHz1.8  65 —thiswork17.7–19.7Dual-loop Discrete 11.29  81 @10 KHz0–5.5  57 51.83 dBTable 1. Performance comparison between various synthesizer structures. 1 2 3 4ABCD4321DCBA TitleNumber RevisionSizeBDate: 10-Nov-2007 Sheet    of File: H:\sotoodeh\sy nthesizer papers\sy nth_18.ddb Drawn By :C17R9R7R10R6C16C20R1C6C67C21 C62R8C15R5C8R11R12C14C3 C4C5++++-Cext13S_Data4S_Clk5S_WR3LD14Dout15PD_D17PD_U18VDD1VDD9VDD16GND6GND12GND19Fin10Fin-11Fr20U2AC2C9C22+C1S-DATS-CLKS-WRS-LD1423coup1N/C6N/C5N/C4N/C3N/C2N/C1N/C7N/C8N/C9N/C10N/C11N/C12N/C24N/C23VTUNE222121VCC20N/C19N/C18N/C17RF OUT16GND15N/C14N/C13GND25U4R4R15R2R3C13R18R17R16C52C10C11 C12C65IN5N/C6IN7GND8OUT1NC2OUT3VCC4GND9U5C60R5014dBmL1L2L5C667GND8out241356U1VCC1VCC2VCC2LOVCC2VCC3VCC46-2+34718U3Figure 6. The LO PLL circuit schematic.Brought to you by | University of Malaya Medical Library (University of Malaya Medical Library)Authenticated | 172.16.1.226Download Date | 7/27/12 6:53 AM34 M. Moghavvemi, H. Ameri and A. AttaranOffset frequency Phase noise (dBc/Hz)1 KHz  7010 KHz  96100 KHz  1181 MHz  138Table 2. VCO phase noise versus offset frequency.Offset frequency Phase noise (dBc/Hz)1 KHz  5510 KHz  85100 KHz  1101 MHz  125Table 3. Xtal phase noise versus offset frequency.the IF PLL is indicated in Figure 5. In the LO PLL, the ref-erence frequency is generated by another TCXO, a productof RAKON Inc., to have a very low noise and high stabil-ity of 5 PPM. The phase noise versus offset is presentedin Table 3 for this chip. The applied PD in the loop is thesame chip as described in the previous section. An MMICis selected for the VCO block. The MMIC has an operationfrequency range of 7.8–8.7 GHz and is capable of changingthe output frequency by a tune voltage of 1–11 v range. A10 dB directional coupler is used to sample the output fre-quency, since the power level of the output is high enough(14 dBm). The sampled frequency is passed through a fre-quency divider, so fin D fLO=4.The selected chip for the frequency divider block hasa very low noise. Its operation frequency range is fromDC to 12.5 GHz and its supply voltage and current are 5 v,100 mA, respectively. In the fabricated synthesizer, M andR are set to 4 and 83, to provide the LO output signal fre-quency fLO:fLO4D MRfr H) fLO D 8300 MHz : (15)The schematic diagram of the LO PLL is shown in Figure 6.Finally, the IF and LO signals are applied to a sub har-monic mixer in order to generate the required frequency.The sub harmonic mixer MMIC has a LO internal ampli-fier and its conversion loss is equal to 10 dB. The frequencyranges of IF and LO signals of this chip are DC 3 GHz and7–10.5 GHz respectively.Considering the sub harmonic mixer characteristic, theoutput signal frequency will be equal tofout D 2  fLO C fin D 17706 MHz : (16)Figure 7 illustrates the schematic of the sub harmonic mixer.The phase noise of the fabricated synthesizer is measuredand presented in the next section. 1 2 3 4ABCD4321DCBATitleNumber RevisionSizeBDate: 10-Nov-2007 Sheet    of File: H:\sotoodeh\sy nthesizer papers\sy nth_18.ddb Drawn By :C24C23OUTRF5IF4VDD3LO6GND1GND2GND7U6IFLOVCC2Figure 7. Modeled mixer circuit schematic.4 Fabrication and Measurement ResultsThe synthesizer is fabricated and shown in Figure 8. TheLO and IF PLL loop’s VCOs have a phase noise around 90 dBc/Hz and  96 dBc/Hz at 10 KHz offset, respec-tively, according to their datasheets. The phase noise ofthe LO signal decreases by 10log2 factor, after multiply-ing by 2 in the sub harmonic mixer. Therefore, there aretwo signals at the sub harmonic mixer inputs: a signal withfrequency of 2  fLO and  87 dBc/Hz phase noise, and anIF signal with  96 dBc/Hz phase noise. The output signalphase noise follows the 2fLO signal phase noise consider-ing the higher phase noise of the IF signal. So a phase noiseof  84 dBc/Hz is predicted for output signal because of thesub harmonic mixer characteristic.Measurement results of the fabricated synthesizer areshown in Figure 9. The frequency spectrum is observedby an HP8563A spectrum analyzer. The frequency span,RBW, and VBW are set to 50 KHz, 1 KHz, and 30 Hz, re-spectively. The difference between carrier and 10 KHz off-set power level is equal to  51.83 dB, as indicated in Fig-ure 9. Thus the phase noise of the output signal is obtainedby the following relation ([10, 11]):Measured phases noise D  51:83–10 logRBWD  81:83 dBc/Hz: (17)Phase noise at 1 KHz and 100 KHz offset are  60 and 100 dBc/Hz, respectively. Spur frequency contents aremeasured at  57 dBc. The predicted performance parame-ters such as gain, spur contents and phase noise are in com-parable to the measured results. The comparison results in-dicate that the phase noise of the system is superior to itsrivals.5 ConclusionThe modeling representations of all intrinsic phase noisespectrum sources of frequency synthesizer loop are dis-cussed. The block-circuit analysis of a dual-loop synthe-sizer is presented. A carefully calculated frequency resolu-tions and design parameters in each loop are analyzed. ThisBrought to you by | University of Malaya Medical Library (University of Malaya Medical Library)Authenticated | 172.16.1.226Download Date | 7/27/12 6:53 AMA Compact Analytical Design of Dual-Loop 18 GHz Frequency Synthesizer 35 Figure 8. The fabricated synthesizer.method is proposed to dramatically reduce the phase noiseeffect in output oscillating frequency due to performancetrade-offs in all the other synthesizer loop structures. Inthis paper, the methodology analysis of dual-loop frequencysynthesizer and spur frequency contents and phase noise areanalyzed. The performance comparison between the pro-posed method and previous works in this frequency is pre-sented. The channel switching is fully programmable for17.7–19.7 GHz frequency range. Test results indicate thatthe fabricated synthesizer has a phase noise of  81 dBc/Hz,much superior to the phase noise reported in the references.AcknowledgmentsThe first author was supported by the Center of Researchin Applied Electronics CRAE. The second author was sup-ported by the University of Malaya.References[1] N. M. Filiol et al., An agile ISM band frequency synthesizerwith built-in GMSK data modulation, IEEE Journal of Solid-State Circuits 33 (1998), no. 7, 998–1008.[2] T. A. D. Riley, M. A. Copeland and T. A. Kwasniewski,Delta-sigma modulation in fractional-N frequency synthe-sis, IEEE Journal of Solid-State Circuits 28 (1993), no. 28,553–559.[3] A. Attaran, M. Moghavvemi and H. Ameri, Design a 14 to20GHz stable source, Microwave and RF 49 (2010), 62–66.[4] M. H. Perrott, T. L. Tewksbury and C. G. Sodini, A 27 mWCMOS fractional-N synthesizer/modulator IC, Solid-StateCircuits Conference 1997, Digest of Technical Papers, 43rdISSCC, 1997 IEEE International, 1997.[5] S. A. Osmany, F. Herzel, J. C. Scheytt, K. Schmalz and W.Winkler, An integrated 19-GHz low-phase-noise frequencysynthesizer in SiGeBiCMOS technology, IEEE CompoundSemiconductor Integrated Circuit Symposium, TechnologyDigest, pp. 191–194, 2007.[6] F. Herzel, S. A. Osmany and J. C. Scheytt, Analytical Phase-Noise Modeling and Charge Pump Optimization for Frac-tional PLLs, IEEE Transactions on Circuits and Systems IRegular Papers (2010), PP(99), 1. Figure 9. The measurement result.[7] A. Attaran, H. Ameri and M. Moghavvemi, Design an X-band frequency synthesizer, Microwaves and RF 49 (2010),98-103.[8] L. Lascari, Accurate Phase Noise Prediction in PLL Syn-thesizers Part 2: Here is a method that uses more completemodeling for wireless applications, Applied Microwave &Wireless 12 (2000), no. 5, 90–94.[9] A. Natarajan, A. Komijani and A. Hajimiri, A fully inte-grated 24-GHz phased-array transmitter in CMOS, IEEEJournal of Solid-State Circuits 40 (2005), no. 11, 2502–2514.[10] P. Yu-Hsun and L. Liang-Hung, A 16-GHz Triple-ModulusPhase-Switching Prescaler and Its Application to a 15-GHzFrequency Synthesizer in 0.18um CMOS, IEEE Transac-tions on Microwave Theory and Techniques 55 (2007), no.1, 44–51.[11] J. Mondal et al., A highly integrated multifunction macrosynthesizer chip (MMSC) for applications in 2–18 GHz syn-thesized sources, IEEE Journal of Solid-State Circuits 32(1997), no. 8, 1405–1409.[12] A. W. L. Ng and H. C. Luong, A 1-V 17-GHz 5-mW CMOSQuadrature VCO Based on Transformer Coupling, IEEEJournal of Solid-State Circuits 42 (2007), no. 8, 1933–1941.[13] T. Geum-Young et al., A 6.3–9-GHz CMOS fast settling PLLfor MB-OFDM UWB applications, IEEE Journal of Solid-State Circuits 40 (2005), no. 7, 1671–1679.[14] T. H. Lin and Y. J. Lai, An Agile VCO Frequency CalibrationTechnique for a 10-GHz CMOS PLL, IEEE Journal of Solid-State Circuits 42 (2007), no. 2, 340–349.[15] V. Jain et al., A Single-Chip Dual-Band 22–29-GHz/77–81-GHz BiCMOS Transceiver for Automotive Radars, IEEEJournal of Solid-State Circuits 44 (2009), no. 11, 3469–3485.[16] A. W. L. Ng et al., A 1-V 24-GHz 17.5-mW phase-lockedloop in a 0.18um CMOS process, IEEE Journal of Solid-State Circuits 41 (2006), no. 6, 1236–1244.[17] Z. Hui et al., A 3.1 GHz to 8.0 GHz Single-Chip Transceiverfor MB-OFDM UWB in 0.18 um CMOS Process, IEEEJournal of Solid-State Circuits 44 (2009), no. 2, 414–426.[18] B. A. Floyd, A 16–18.8-GHz Sub-Integer-N Frequency Syn-thesizer for 60-GHz Transceivers, IEEE Journal of Solid-State Circuits 43 (2008), no. 5, 1076–1086.Brought to you by | University of Malaya Medical Library (University of Malaya Medical Library)Authenticated | 172.16.1.226Download Date | 7/27/12 6:53 AM

A Compact Analytical Design of Dual-Loop 18 GHz Frequency Synthesizer to Enhance Signal Reliability in Digital Millimeter Radio Link System

In this paper a high resolution dual-loop 17.7-19.7 GHz frequency synthesizer is presented which is compatible with ITU-R (F.595-6) standards. The investigations of phase noise and spur frequency contents are discussed in detail. The simulated and measured phase noise and spur frequency contents are similar to one another. Phase noise of -81 dBc/Hz in 17.7 GHz at 10 KHz offset frequency is measured by (HP8560) series Spectrum analyzer and it matches with predicted measurements

Ameri Mahabadi, H.

UM Digital Repository

A compact analytical design of dual-loop 18 GHz frequency synthesizer to enhance signal reliability in digital millimeter radio link system

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A Compact Analytical Design of Dual-Loop 18 GHz Frequency Synthesizer to Enhance Signal Reliability in Digital Millimeter Radio Link System

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