Using a Second Order Sigma-Delta Control to Improve the Performance of Metal-Oxide Gas Sensors

Controls of surface potential have been proposed to accelerate the time response of MOX gas sensors. These controls use temperature modulations and a feedback loop based on first-order sigma-delta modulators to keep constant the surface potential. Changes in the surrounding gases, therefore, must be compensated by average temperature produced by the control loop, which is the new output signal. The purpose of this paper is to present a second order sigma-delta control of the surface potential for gas sensors. With this new control strategy, it is possible to obtain a second order zero of the quantization noise in the output signal. This provides a less noisy control of the surface potential, while at the same time some undesired effects of first order modulators, such as the presence of plateaus, are avoided. Experiments proving these performance improvements are presented using a gas sensor made of tungsten oxide nanowires. Plateau avoidance and second order noise shaping is shown with ethanol measurements.Postprint (author's final draft

Tools for Automated Design of ΣΔ Modulators

We present a set of CAD tools to design ΣΔ modulators. They use statistical optimization to calculate optimum specifications for the building blocks used in the modulators, and optimum sizes for the components in these blocks. Optimization procedures at the modulator level are equation-based, while procedures at the cell level are simulation-based. The toolset incorporates also an advanced ΣΔ behavioral simulator for monitoring and design space exploration. We include measurements taken from two silicon prototypes: 1) a 17bit@40kHz output rate fourth-order low-pass modulator; and 2) a [email protected] central freq@10kHz bandwidth band-pass modulator. The first uses SC fully-differential circuits in a 1.2μm CMOS double-metal double-poly technology. The second uses SI fully-differential circuits in a 0.8μm CMOS double-metal single-poly technology.This work has been supported by the CEE ESPRIT Program in the framework of the Project #8795 (AMFIS).Peer reviewe

Tools for Automated Design of ΣΔ Modulators

We present a set of CAD tools to design ΣΔ modulators. They use statistical optimization to calculate optimum specifications for the building blocks used in the modulators, and optimum sizes for the components in these blocks. Optimization procedures at the modulator level are equation-based, while procedures at the cell level are simulation-based. The toolset incorporates also an advanced ΣΔ behavioral simulator for monitoring and design space exploration. We include measurements taken from two silicon prototypes: 1) a 17bit@40kHz output rate fourth-order low-pass modulator; and 2) a [email protected] central freq@10kHz bandwidth band-pass modulator. The first uses SC fully-differential circuits in a 1.2μm CMOS double-metal double-poly technology. The second uses SI fully-differential circuits in a 0.8μm CMOS double-metal single-poly technology

State scaling of continuous-time sigma-delta modulators

In this paper, the common method of scaling the feedback coefficients of continuous time sigma delta modulators in order to stabilize the system is enhanced. The presented approach scales the different states of the system instead of the coefficients. The new corresponding coefficients are then calculated from the solution of the state space description. Therewith, it is possible to tune the maximum out-of-band gain directly in continuous time. In addition, the input amplitude distribution between each quantization level of multi bit sigma-delta modulator can be adapted

Design of passive SD modulator for ESP32

This thesis addresses the problem of voice recognition, by studying how to build a lowcost solution for data acquisition, presents the analysis, design implementation and simulation of a low-cost continuous-time(CT) passive sigma-delta modulator(SDM) with signal-to-noise-plus-distortion ratio(SNDR) > 86dB to increase fidelity in voice recognition applications. Employing passive RC integrators and a differential signal structure, the CT passive SDM is optimized to work as independently from a specific comparator module as possible, by decreasing the necessary gain of the comparator in the modulator gain. Nevertheless, the loop gain is restricted by the comparator’s noise, aggravated by the high attenuation of the passive RC integrators on the signal, causing low voltage swing at the comparator’s input. It is discussed the viability of utilizing a microprocessor (μP) as substitute of the comparator block in a CT passive SDM, specifically, the esp32. Due to hardware limitations and the high-frequency requirements of the CT passive SDM, it is proven this substitution is not viable. Along the course of the design implementation a comparison in the performance of three different simulation software is presented, these software being, the open-source LTspice VII, the open-source Ngspice and the private Cadence Virtuoso. As it was necessary to change simulation software at different stages in the design of the circuit

Design, analysis and evaluation of sigma-delta based beamformers for medical ultrasound imaging applications

The inherent analogue nature of medical ultrasound signals in conjunction with the abundant merits provided by digital image acquisition, together with the increasing use of relatively simple front-end circuitries, have created considerable demand for single-bit beamformers in digital ultrasound imaging systems. Furthermore, the increasing need to design lightweight ultrasound systems with low power consumption and low noise, provide ample justification for development and innovation in the use of single-bit beamformers in ultrasound imaging systems. The overall aim of this research program is to investigate, establish, develop and confirm through a combination of theoretical analysis and detailed simulations, that utilize raw phantom data sets, suitable techniques for the design of simple-to-implement hardware efficient digital ultrasound beamformers to address the requirements for 3D scanners with large channel counts, as well as portable and lightweight ultrasound scanners for point-of-care applications and intravascular imaging systems. In addition, the stability boundaries of higher-order High-Pass (HP) and Band-Pass (BP) Σ−Δ modulators for single- and dual- sinusoidal inputs are determined using quasi-linear modeling together with the describing-function method, to more accurately model the modulator quantizer. The theoretical results are shown to be in good agreement with the simulation results for a variety of input amplitudes, bandwidths, and modulator orders. The proposed mathematical models of the quantizer will immensely help speed up the design of higher order HP and BP Σ−Δ modulators to be applicable for digital ultrasound beamformers. Finally, a user friendly design and performance evaluation tool for LP, BP and HP modulators is developed. This toolbox, which uses various design methodologies and covers an assortment of modulators topologies, is intended to accelerate the design process and evaluation of modulators. This design tool is further developed to enable the design, analysis and evaluation of beamformer structures including the noise analyses of the final B-scan images. Thus, this tool will allow researchers and practitioners to design and verify different reconstruction filters and analyze the results directly on the B-scan ultrasound images thereby saving considerable time and effort

Methods and Devices for Modifying Active Paths in a K-Delta-1-Sigma Modulator

The invention relates to an improved K-Delta-1-Sigma Modulators (KG1Ss) that achieve multi GHz sampling rates with 90 nm and 45 nm CMOS processes, and that provide the capability to balance performance with power in many applications. The improved KD1Ss activate all paths when high performance is needed (e.g. high bandwidth), and reduce the effective bandwidth by shutting down multiple paths when low performance is required. The improved KD1Ss can adjust the baseband filtering for lower bandwidth, and can provide large savings in power consumption while maintaining the communication link, which is a great advantage in space communications. The improved KD1Ss herein provides a receiver that adjusts to accommodate a higher rate when a packet is received at a low bandwidth, and at a initial lower rate, power is saved by turning off paths in the KD1S Analog to Digital Converter, and where when a higher rate is required, multiple paths are enabled in the KD1S to accommodate the higher band widths

Rapid Prototyping of Third-Order Sigma-Delta A/D Converters

Prototyping of third-order sigma-delta analog to digital converters (ƩΔADCs) has been presented in the paper. The method is based on implementation of field programmable analog arrays (FPAA) to configure and reconfigure proposed circuits. Three third-order ƩΔ ADC structures have been considered. The circuit characteristics have been measured and then the structure of the converters have been reconfigured to satisfy input specifications