Software and hardware implementation techniques for digital communications-related algorithms

There are essentially three areas addressed in the body of this thesis. (a) The first is a theoretical investigation into the design and development of a practically realizable implementation of a maximum-likelihood detection process to deal with digital data transmission over HF radio links. These links exhibit multipath properties with delay spreads that can easily extend over 12 to 15 milliseconds. The project was sponsored by the Ministry of Defence through the auspices of the Science and Engineering Research Council. The primary objective was to transmit voice band data at a minimum rate of 2.4 kb/s continuously for long periods of time during the day or night. Computer simulation models of HF propagation channels were created to simulate atmospheric and multipath effects of transmission from London to Washington DC, Ankara, and as far as Melbourne, Australia. Investigations into HF channel estimation are not the subject of this thesis. The detection process assumed accurate knowledge of the channel. [Continues.

Design Sign of Delta Sigma Wattmeter

Instantaneous power in a load is measured by multiplying the voltage across it by the current flowing through it. The multiplication is achieved in a delta sigma wattmeter by using two samplers rather than a multiplier. Sampling and multiplication are closely related. For example, double side-band suppressed carrier modulation can be produced by either multiplying an analogue signal with a sinusoidal carrier, or by sampling the analogue signal with a binary pulse train and filtering these samples. Alternatively these samples can be produced without a sampler if a multiplier is used. This is achieved by multiplying pulse train, whose binary values are arranged to be zero or unity, with the analogue signal. The delta-sigma wattmeter is given this name because the voltage developed across the load in which the power is to be measured is encoded by a delta sigma modulator, d.s.m into a binary waveform. The d.s.m. decoder is just a low-pass filte

Universal Digital Controller for Boost CCM Power Factor Correction Stages Based on Current Rebuilding Concept

Continuous conduction mode power factor correction (PFC) without input current measurement is a step forward with respect to previously proposed PFC digital controllers. Inductor volt-second (vsL) measurement in each switching period enables digital estimation of the input current; however, an accurate compensation of the small errors in the measured vsL is required for the estimation to match the actual current. Otherwise, they are accumulated every switching period over the half-line cycle, leading to an appreciable current distortion. A vsL estimation method is proposed, measuring the input (vg) and output voltage (vo). Discontinuous conduction mode (DCM) occurs near input line zero crossings and is detected by measuring the drain-to-source MOSFET voltage vds. Parasitic elements cause a small difference between the estimated voltage across the inductor based on input and output voltage measurements and the actual one, which must be taken into account to estimate the input current in the proposed sensorless PFC digital controller. This paper analyzes the current estimation error caused by errors in the ON-time estimation, voltage measurements, and the parasitic elements. A new digital feedback control with high resolution is also proposed. It cancels the difference between DCM operation time of the real input current, (TDCMg) and the estimated DCM time (TDCMreb). Therefore, the current estimation is calibrated using digital signals during operation in DCM. A fast feedforward coarse time error compensation is carried out with the measured delay of the drive signal, and a fine compensation is achieved with a feedback loop that matches the estimated and real DCM time. The digital controller can be used in universal applications due to the ability of the DCM time feedback loop to autotune based on the operation conditions (power level, input voltage, output v- ltage...), which improves the operation range in comparison with previous solutions. Experimental results are shown for a 1-kW boost PFC converter over a wide power and voltage range

Power quality enhancement in residential smart grids through power factor correction stages

The proliferation of non-linear loads and the increasing penetration of Distributed Energy Resources (DER) in Medium-Voltage (MV) and Low-Voltage (LV) distribution grids, make it more difficult to maintain the power quality levels in residential electrical grids, especially in the case of weak grids. Most household appliances contain a conventional Power Factor Corrector (PFC) rectifier, which maximizes the load Power Factor (PF) but does not contribute to the regulation of the voltage Total Harmonic Distortion (THDV) in residential electrical grids. This manuscript proposes a modification for PFC controllers by adapting the operation mode depending on the measured THDV. As a result, the PFCs operate either in a low current Total Harmonic Distortion (THDI) mode or in the conventional resistor emulator mode and contribute to the regulation of the THDV and the P F at the distribution feeders. To prove the concept, the modification is applied to a current sensorless Non-Linear Controller (NLC) applied to a single-phase Boost rectifier. Experimental results show its performance in a PFC front-end stage operating in Continuous Conduction Mode (CCM) connected to the grid with different THDV.This work is funded by the Spanish Ministry of Science and Innovation through the project TEC2014-52316-R ECOTREND Estimation and Optimal Control for Energy Conversion with Digital Devices

A Phase-Angle Tracking Method for Synchronization of Single- and Three-Phase Grid-Connected Converters

This thesis proposes a phase-angle tracking method, i.e., based on discrete Fourier transform for synchronization of three-phase and single-phase power-electronic converters under distorted and variable-frequency conditions. The proposed methods are designed based on fixed sampling rate and, thus, they can simply be employed for control applications. For three-phase applications, first, analytical analysis are presented to determine the errors associated with the phasor estimation using standard full-cycle discrete Fourier transform in a variable-frequency environment. Then, a robust phase-angle estimation technique is proposed, which is based on a combination of estimated positive and negative sequences, tracked frequency, and two proposed compensation coefficients. The proposed method has one cycle transient response and is immune to harmonics, noises, voltage imbalances, and grid frequency variations. An effective approximation technique is proposed to simplify the computation of the compensation coefficients. The effectiveness of the proposed method is verified through a comprehensive set of simulations in Matlab software. Simulation results show the robust and accurate performance of the proposed method in various abnormal operating conditions. For single-phase applications, an accurate phasor-estimation method is proposed to track the phase-angle of fundamental frequency component of voltage or current signals. This method can be used in three-phase applications as well. The proposed method is based on a fixed sampling frequency and, thus, it can simply be integrated in control applications of the grid-connected converters. Full-cycle discrete Fourier transform (DFT) is adopted as a base for phasor estimation. Two procedures are taken to effectiveness reduce the phasor estimation error using DFT during o - nominal frequency operation. First, adaptive window length (AWL) is applied to match the window-length of the DFT with respect to the input signal frequency. As AWL can partially reduce the error if sampling rate is not high, phasor compensation is employed to compensate the remaining error in the estimated phasor. Both procedures require system frequency, thus, an effective frequency-estimation technique is proposed to obtain fast and accurate performance. The proposed method has one cycle transient response and is immune to harmonics, noises, and grid frequency variations. The effectiveness of the proposed method is verified through a comprehensive set of simulations in Matlab and hardware implementation test using real-time digital signal processor data acquisition system

Analog dithering techniques for highly linear and efficient transmitters

The current thesis is about investigation of new methods and techniques to be able to utilize the switched mode amplifiers, for linear and efficient applications. Switched mode amplifiers benefit from low overlap between the current and voltage wave forms in their output terminals, but they seriously suffer from nonlinearity. This makes it impossible to use them to amplify non-constant envelope message signals, where very high linearity is expected. In order to do that, dithering techniques are studied and a full linearity analysis approach is developed, by which the linearity performance of the dithered amplifier can be analyzed, based on the dithering level and frequency. The approach was based on orthogonalization of the equivalent nonlinearity and is capable of prediction of both co-channel and adjacent channel nonlinearity metrics, for a Gaussian complex or real input random signal. Behavioral switched mode amplifier models are studied and new models are developed, which can be utilized to predict the nonlinear performance of the dithered power amplifier, including the nonlinear capacitors effects. For HFD application, self-oscillating and asynchronous sigma delta techniques are currently used, as pulse with modulators (PWM), to encode a generic RF message signal, on the duty cycle of an output pulse train. The proposed models and analysis techniques were applied to this architecture in the first phase, and the method was validated with measurement on a prototype sample, realized in 65 nm TSMC CMOS technology. Afterwards, based on the same dithering phenomenon, a new linearization technique was proposed, which linearizes the switched mode class D amplifier, and at the same time can reduce the reactive power loss of the amplifier. This method is based on the dithering of the switched mode amplifier with frequencies lower than the band-pass message signal and is called low frequency dithering (LFD). To test this new technique, two test circuits were realized and the idea was applied to them. Both of the circuits were of the hard nonlinear type (class D) and are integrated CMOS and discrete LDMOS technologies respectively. The idea was successfully tested on both test circuits and all of the linearity metric predictions for a digitally modulated RF signal and a random signal were compared to the measurements. Moreover a search method to find the optimum dither frequency was proposed and validated. Finally, inspired by averaging interpretation of the dithering phenomenon, three new topologies were proposed, which are namely DLM, RF-ADC and area modulation power combining, which are all nonlinear systems linearized with dithering techniques. A new averaging method was developed and used for analysis of a Gilbert cell mixer topology, which resulted in a closed form relationship for the conversion gain, for long channel devices

Tehomuuntajan säädön toteutus FPGA:lla

High switching frequencies and control rates in switched-mode power supplies are hard to implement with microcontrollers. Very high clock frequency is required to execute complex control algorithms with high control rate. FPGA chips offer a solution with inherent parallel processing. In this thesis, the feasibility of implementing the control of a typical telecom power converter with FPGA is studied. Requirements for the control system partitioning are considered. The control of a resonant LLC converter is studied in detail and implemented in VHDL. As part of the controller, a high-resolution variable frequency PWM module and floating-point arithmetic modules are implemented. Finally, a complete VHDL simulation model is created and run in different conditions to verify the functionality of the design.Korkeat kytkentä- ja säätötaajuudet hakkuriteholähteissä ovat haastavia toteuttaa mikrokontrollereilla. Monimutkaiset säätöalgoritmit edellyttävät mikrokontrollereilta korkeaa kellotaajuutta. FPGA-teknologia mahdollistaa rinnakkaislaskennan, joka on etu säätösovelluksissa. Tässä työssä tutkitaan FPGA teknologian soveltumista tyypillisen telecom-tehomuuntajan säätöön. Työssä selvitetään säätöjärjestelmän partitiointia sekä toteutetaan LLC-muuntajan ja sen säätöjärjestelmän simulaatiomalli VHDL-kielellä. Säädön osana toteutetaan korkearesoluutioinen PWM-moduuli sekä liukulukuaritmetiikkamoduuleja

Signal Encoding and Digital Signal Processing in Continuous Time

This work investigates signal encoding in, and architectures of, digital signal processing systems that function in continuous time (CT). Unlike conventional digital signal processors (DSPs), which rely on a clock to dictate the sampling times of an analog-to-digital converter (ADC) and to provide the tap delay timing, CT DSPs function entirely in continuous time, without a sampling or a synchronizing clock. The samples of a CT DSP system are generated and processed only when some measure of the input signal crosses a predetermined threshold. The effective sampling rate and the dynamic power dissipation of a CT digital system automatically adapt to the activity of the input signal. The properties of signals sampled in continuous time are investigated in this thesis. A technique for reducing the effective sampling rate of a CT system is presented, in which the digital signal encoding is varied by adjusting the resolution according to a property of the input. A variable-resolution system leads to a decrease in the number of samples generated, a reduction in the power dissipation and a reduction in the effective chip area of a CT DSP, all without sacrificing in-band performance. The properties of several asynchronous signal-driven sampling techniques are analyzed and compared. The architecture and signal encoding of CT DSPs for signals in the lower gigahertz frequency range are investigated, with consideration of speed and accuracy limitations in the context of submicron CMOS technologies. A per-edge digital signal encoding technique is developed, which bypasses timing problems of processing high-speed digital signals; the properties of per-edge encoded signals are discussed. The design considerations of a low-resolution per-edge-encoded gigahertz-range CT DSP are discussed and an implementation for a possible application is detailed. A prototype chip has been fabricated in ST 65 nm CMOS technology, which has a compact processor core area of 0.073 mm^2. The implemented CT digital processor achieves SNDR of over 20 dB with 3 bits of resolution and a maximum usable -3 dB bandwidth of 0.8 GHz to 3.2 GHz. The processor can be configured as a one-tap to six-tap CT FIR filter and has an active power dissipation that varies from 0.27 mW to 9.5 mW, depending on the amplitude and frequency of the input signal

Optical Communication with Semiconductor Laser Diode

Theoretical and experimental performance limits of a free-space direct detection optical communication system were studied using a semiconductor laser diode as the optical transmitter and a silicon avalanche photodiode (APD) as the receiver photodetector. Optical systems using these components are under consideration as replacements for microwave satellite communication links. Optical pulse position modulation (PPM) was chosen as the signal format. An experimental system was constructed that used an aluminum gallium arsenide semiconductor laser diode as the transmitter and a silicon avalanche photodiode photodetector. The system used Q=4 PPM signaling at a source data rate of 25 megabits per second. The PPM signal format requires regeneration of PPM slot clock and word clock waveforms in the receiver. A nearly exact computational procedure was developed to compute receiver bit error rate without using the Gaussion approximation. A transition detector slot clock recovery system using a phase lock loop was developed and implemented. A novel word clock recovery system was also developed. It was found that the results of the nearly exact computational procedure agreed well with actual measurements of receiver performance. The receiver sensitivity achieved was the closest to the quantum limit yet reported for an optical communication system of this type