A System On Chip Dedicated To Pipeline Neighborhood Processing For Mathematical Morphology

Also available at http://www.eurasip.org/Proceedings/Eusipco/Eusipco2008/papers/1569104317.pdfInternational audienceThis paper describes a system on chip for image processing. It is based on a pipe-line of neighborhood processors named SPoC and is controlled by a general purpose processor. Each SPoC are connected one to the other through a reconfigurable data path to get more adaptability and their structure exploits temporal and spatial parallelism to speed up computations and minimize memory transfers. Two applications, a motion detection algorithm and a licence plate extraction, are presented to show performances in terms of speed, embeddability and re-usability of the SoC. Comparisons with many architectures such as digital signal processors, workstations or embedded SIMD processors are made to benchmark the platform and prove the originality and the strength of our solution

Digital implementation of the cellular sensor-computers

Two different kinds of cellular sensor-processor architectures are used nowadays in various applications. The first is the traditional sensor-processor architecture, where the sensor and the processor arrays are mapped into each other. The second is the foveal architecture, in which a small active fovea is navigating in a large sensor array. This second architecture is introduced and compared here. Both of these architectures can be implemented with analog and digital processor arrays. The efficiency of the different implementation types, depending on the used CMOS technology, is analyzed. It turned out, that the finer the technology is, the better to use digital implementation rather than analog

Fast recursive grayscale morphology operators: from the algorithm to the pipeline architecture

International audienceThis paper presents a new algorithm for an efficient computation of morphological operations for gray images and its specific hardware. The method is based on a new recursive morphological decomposition method of 8-convex structuring elements by only causal two-pixel structuring elements (2PSE). Whatever the element size, erosion or/and dilation can then be performed during a unique raster-like image scan involving a fixed reduced analysis neighborhood. The resulting process offers low computation complexity combined with easy description of the element form. The dedicated hardware is generic and fully regular, built from elementary interconnected stages. It has been synthesized into an FPGA and achieves high frequency performances for any shape and size of structuring element

Stream implementation of serial morphological filters with approximated polygons

ISBN : 978-142448157-6International audienceThis paper describes an original stream implementation of serially composed morphological filters using approximated flat polygons. It strictly respects a sequential data access. Results are obtained with minimal latency while operating within minimal memory space; even for very large neighborhoods. This is interesting for serially composed advanced filters, such as Alternating Sequential Filters or granulometries. We show how the dedicated implementation on an FPGA allows obtaining a previously unequaled performance, opening an opportunity to use these operators in time-critical, high-end applications

An embedded system supporting dynamic partial reconfiguration of hardware resources for morphological image processing

Processors for high-performance computing applications are generally designed with a focus on high clock rates, parallelism of operations and high communication bandwidth, often at the expense of large power consumption. However, the emphasis of many embedded systems and untethered devices is on minimal hardware requirements and reduced power consumption. With the incessant growth of computational needs for embedded applications, which contradict chip power and area needs, the burden is put on the hardware designers to come up with designs that optimize power and area requirements. This thesis investigates the efficient design of an embedded system for morphological image processing applications on Xilinx FPGAs (Field Programmable Gate Array) by optimizing both area and power usage while delivering high performance. The design leverages a unique capability of FPGAs called dynamic partial reconfiguration (DPR) which allows changing the hardware configuration of silicon pieces at runtime. DPR allows regions of the FPGA to be reprogrammed with new functionality while applications are still running in the remainder of the device. The main aim of this thesis is to design an embedded system for morphological image processing by accounting for real time and area constraints as compared to a statically configured FPGA. IP (Intellectual Property) cores are synthesized for both static and dynamic time. DPR enables instantiation of more hardware logic over a period of time on an existing device by time-multiplexing the hardware realization of functions. A comparison of power consumption is presented for the statically and dynamically reconfigured designs. Finally, a performance comparison is included for the implementation of the respective algorithms on a hardwired ARM processor as well as on another general-purpose processor. The results prove the viability of DPR for morphological image processing applications

P2IP: A novel low-latency Programmable Pipeline Image Processor

International audienceThis paper presents a novel systolic Coarse-Grained Reconfigurable Architecture for real-time image and video processing called P 2 IP. The P 2 IP is a scalable architecture that combines the low-latency characteristic of systolic array architectures with a runtime reconfigurable datapath. Reconfigurabil-ity of the P 2 IP enables it to perform a wide range of image pre-processing tasks directly on a pixel stream. The versatility of the P 2 IP is demonstrated through three image processing algorithms mapped onto the architecture, implemented in an FPGA-based platform. The obtained results show that the P 2 IP can achieve up to 129 fps in Full HD 1080p and 32 fps in 4K 2160p what makes it suitable for modern high-definition applications

The Hyper Suprime-Cam Software Pipeline

In this paper, we describe the optical imaging data processing pipeline developed for the Subaru Telescope's Hyper Suprime-Cam (HSC) instrument. The HSC Pipeline builds on the prototype pipeline being developed by the Large Synoptic Survey Telescope's Data Management system, adding customizations for HSC, large-scale processing capabilities, and novel algorithms that have since been reincorporated into the LSST codebase. While designed primarily to reduce HSC Subaru Strategic Program (SSP) data, it is also the recommended pipeline for reducing general-observer HSC data. The HSC pipeline includes high level processing steps that generate coadded images and science-ready catalogs as well as low-level detrending and image characterizations.Comment: 39 pages, 21 figures, 2 tables. Submitted to Publications of the Astronomical Society of Japa

The Boston University Photonics Center annual report 2015-2016

This repository item contains an annual report that summarizes activities of the Boston University Photonics Center in the 2015-2016 academic year. The report provides quantitative and descriptive information regarding photonics programs in education, interdisciplinary research, business innovation, and technology development. The Boston University Photonics Center (BUPC) is an interdisciplinary hub for education, research, scholarship, innovation, and technology development associated with practical uses of light.This has been a good year for the Photonics Center. In the following pages, you will see that this year the Center’s faculty received prodigious honors and awards, generated more than 100 notable scholarly publications in the leading journals in our field, and attracted $18.9M in new research grants/contracts. Faculty and staff also expanded their efforts in education and training, and cooperated in supporting National Science Foundation sponsored Sites for Research Experiences for Undergraduates and for Research Experiences for Teachers. As a community, we emphasized the theme of “Frontiers in Plasmonics as Enabling Science in Photonics and Beyond” at our annual symposium, hosted by Bjoern Reinhard. We continued to support the National Photonics Initiative, and contributed as a cooperating site in the American Institute for Manufacturing Integrated Photonics (AIM Photonics) which began this year as a new photonics-themed node in the National Network of Manufacturing Institutes. Highlights of our research achievements for the year include an ambitious new DoD-sponsored grant for Development of Less Toxic Treatment Strategies for Metastatic and Drug Resistant Breast Cancer Using Noninvasive Optical Monitoring led by Professor Darren Roblyer, continued support of our NIH-sponsored, Center for Innovation in Point of Care Technologies for the Future of Cancer Care led by Professor Cathy Klapperich, and an exciting confluence of new grant awards in the area of Neurophotonics led by Professors Christopher Gabel, Timothy Gardner, Xue Han, Jerome Mertz, Siddharth Ramachandran, Jason Ritt, and John White. Neurophotonics is fast becoming a leading area of strength of the Photonics Center. The Industry/University Collaborative Research Center, which has become the centerpiece of our translational biophotonics program, continues to focus onadvancing the health care and medical device industries, and has entered its sixth year of operation with a strong record of achievement and with the support of an enthusiastic industrial membership base