High Performance RF and Basdband Analog-to-Digital Interface for Multi-standard/Wideband Applications

The prevalence of wireless standards and the introduction of dynamic standards/applications, such as software-defined radio, necessitate the next generation wireless devices that integrate multiple standards in a single chip-set to support a variety of services. To reduce the cost and area of such multi-standard handheld devices, reconfigurability is desirable, and the hardware should be shared/reused as much as possible. This research proposes several novel circuit topologies that can meet various specifications with minimum cost, which are suited for multi-standard applications. This doctoral study has two separate contributions: 1. The low noise amplifier (LNA) for the RF front-end; and 2. The analog-to-digital converter (ADC). The first part of this dissertation focuses on LNA noise reduction and linearization techniques where two novel LNAs are designed, taped out, and measured. The first LNA, implemented in TSMC (Taiwan Semiconductor Manufacturing Company) 0.35Cm CMOS (Complementary metal-oxide-semiconductor) process, strategically combined an inductor connected at the gate of the cascode transistor and the capacitive cross-coupling to reduce the noise and nonlinearity contributions of the cascode transistors. The proposed technique reduces LNA NF by 0.35 dB at 2.2 GHz and increases its IIP3 and voltage gain by 2.35 dBm and 2dB respectively, without a compromise on power consumption. The second LNA, implemented in UMC (United Microelectronics Corporation) 0.13Cm CMOS process, features a practical linearization technique for high-frequency wideband applications using an active nonlinear resistor, which obtains a robust linearity improvement over process and temperature variations. The proposed linearization method is experimentally demonstrated to improve the IIP3 by 3.5 to 9 dB over a 2.5–10 GHz frequency range. A comparison of measurement results with the prior published state-of-art Ultra-Wideband (UWB) LNAs shows that the proposed linearized UWB LNA achieves excellent linearity with much less power than previously published works. The second part of this dissertation developed a reconfigurable ADC for multistandard receiver and video processors. Typical ADCs are power optimized for only one operating speed, while a reconfigurable ADC can scale its power at different speeds, enabling minimal power consumption over a broad range of sampling rates. A novel ADC architecture is proposed for programming the sampling rate with constant biasing current and single clock. The ADC was designed and fabricated using UMC 90nm CMOS process and featured good power scalability and simplified system design. The programmable speed range covers all the video formats and most of the wireless communication standards, while achieving comparable Figure-of-Merit with customized ADCs at each performance node. Since bias current is kept constant, the reconfigurable ADC is more robust and reliable than the previous published works

Analysis of Current Conveyor based Switched Capacitor Circuits for Application in ∆Σ Modulators

The reduction in supply voltage, loss of dynamic range and increased noise prevent the analog circuits from taking advantage of advanced technologies. Therefore the trend is to move all signal processing tasks to digital domain where advantages of technology scaling can be used. Due to this, there exists a need for data converters with large signal bandwidths, higher speeds and greater dynamic range to act as an interface between real world analog and digital signals. The Delta Sigma (∆Σ) modulator is a data converter that makes use of large sampling rates and noise shaping techniques to achieve high resolution in the band of interest. The modulator consists of analog integrators and comparators which create a modulated digital bit stream whose average represents the input value. Due to their simplicity, they are popular in narrow band receivers, medical and sensor applications. However Operational Amplifiers (Op-Amps) or Operational Transconductance Amplifiers (OTAs), which are commonly used in data converters, present a bottleneck. Due to low supply voltages, designers rely on folded cascode, multistage cascade and bulk driven topologies for their designs. Although the two stage or multistage cascade topologies offer good gain and bandwidth, they suffer from stability problems due to multiple stages and feedback requiring large compensation capacitors. Therefore other low voltage Switched-Capacitor (SC) circuit techniques were developed to overcome these problems, based on inverters, comparators and unity gain buffers. In this thesis we present an alternative approach to design of ∆Σ modulators using Second Generation Current Conveyors (CCIIs). The important feature of these modulators is the replacement of the traditional Op-Amp based SC integrators with CCII based SC integrators. The main design issues such as the effect of the non-idealities in the CCIIs are considered in the operation of SC circuits and solutions are proposed to cancel them. Design tradeoffs and guidelines for various components of the circuit are presented through analysis of existing and the proposed SC circuits. A two step adaptive calibration technique is presented which uses few additional components to measure the integrator input output characteristic and linearize it for providing optimum performance over a wide range of sampling frequencies while maintaining low power and area. The presented CCII integrator and calibration circuit are used in the design of a 4th order (2-2 cascade) ∆Σ modulator which has been fabricated in UMC 90nm/1V technology through Europractice. Experimental values for Signal to Noise+Distortion Ratio (SNDR), Dynamic Range (DR) and Figure Of Merit (FOM) show that the modulator can compete with state of art reconfigurable Discrete-Time (DT) architectures while using lower gain stages and less design complexity

Time interleaved counter analog to digital converters

The work explores extending time interleaving in A/D converters, by applying a high-level of parallelism to one of the slowest and simplest types of data-converters, the counter ADC. The motivation for the work is to realise high-performance re-configurable A/D converters for use in multi-standard and multi-PHY communication receivers with signal bandwidths in the 10s to 100s of MHz. The counter ADC requires only a comparator, a ramp signal, and a digital counter, where the comparator compares the sampled input against all possible quantisation levels sequentially. This work explores arranging counter ADCs in large time-interleaved arrays, building a Time Interleaved Counter (TIC) ADC. The key to realising a TIC ADC is distributed sampling and a global multi-phase ramp generator realised with a novel figure-of-8 rotating resistor ring. Furthermore Counter ADCs allow for re-configurability between effective sampling rate and resolution due to their sequential comparison of reference levels in conversion. A prototype TIC ADC of 128-channels was fabricated and measured in 0.13μm CMOS technology, where the same block can be configured to operate as a 7-bit 1GS/s, 8-bit 500MS/s, or 9-bit 250MS/s dataconverter. The ADC achieves a sub 400fJ/step FOM in all modes of configuration

Design of Energy-Efficient A/D Converters with Partial Embedded Equalization for High-Speed Wireline Receiver Applications

As the data rates of wireline communication links increases, channel impairments such as skin effect, dielectric loss, fiber dispersion, reflections and cross-talk become more pronounced. This warrants more interest in analog-to-digital converter (ADC)-based serial link receivers, as they allow for more complex and flexible back-end digital signal processing (DSP) relative to binary or mixed-signal receivers. Utilizing this back-end DSP allows for complex digital equalization and more bandwidth-efficient modulation schemes, while also displaying reduced process/voltage/temperature (PVT) sensitivity. Furthermore, these architectures offer straightforward design translation and can directly leverage the area and power scaling offered by new CMOS technology nodes. However, the power consumption of the ADC front-end and subsequent digital signal processing is a major issue. Embedding partial equalization inside the front-end ADC can potentially result in lowering the complexity of back-end DSP and/or decreasing the ADC resolution requirement, which results in a more energy-effcient receiver. This dissertation presents efficient implementations for multi-GS/s time-interleaved ADCs with partial embedded equalization. First prototype details a 6b 1.6GS/s ADC with a novel embedded redundant-cycle 1-tap DFE structure in 90nm CMOS. The other two prototypes explain more complex 6b 10GS/s ADCs with efficiently embedded feed-forward equalization (FFE) and decision feedback equalization (DFE) in 65nm CMOS. Leveraging a time-interleaved successive approximation ADC architecture, new structures for embedded DFE and FFE are proposed with low power/area overhead. Measurement results over FR4 channels verify the effectiveness of proposed embedded equalization schemes. The comparison of fabricated prototypes against state-of-the-art general-purpose ADCs at similar speed/resolution range shows comparable performances, while the proposed architectures include embedded equalization as well

Integrated Circuit Blocks for High Performance Baseband and RF Analog-to-Digital Converters

Nowadays, the multi-standard wireless receivers and multi-format video processors have created a great demand for integrating multiple standards into a single chip. The multiple standards usually require several Analog to Digital Converters (ADCs) with different specifications. A promising solution is adopting a power and area efficient reconfigurable ADC with tunable bandwidth and dynamic range. The advantage of the reconfigurable ADC over customized ADCs is that its power consumption can be scaled at different specifications, enabling optimized power consumption over a wide range of sampling rates and resulting in a more power efficient design. Moreover, the reconfigurable ADC provides IP reuse, which reduces design efforts, development costs and time to market. On the other hand, software radio transceiver has been introduced to minimize RF blocks and support multiple standards in the same chip. The basic idea is to perform the analog to digital (A/D) and digital to analog (D/A) conversion as close to the antenna as possible. Then the backend digital signal processor (DSP) can be programmed to deal with the digital data. The continuous time (CT) bandpass (BP) sigma-delta ADC with good SNR and low power consumption is a good choice for the software radio transceiver. In this work, a proposed 10-bit reconfigurable ADC is presented and the non-overlapping clock generator and state machine are implemented in UMC 90nm CMOS technology. The state machine generates control signals for each MDAC stage so that the speed can be reconfigured, while the power consumption can be scaled. The measurement results show that the reconfigurable ADC achieved 0.6-200 MSPS speed with 1.9-27 mW power consumption. The ENOB is about 8 bit over the whole speed range. In the second part, a 2-bit quantizer with tunable delay circuit and 2-bit DACs are implemented in TSMC 0.13um CMOS technology for the 4th order CT BP sigma-delta ADC. The 2-bit quantizer and 2-bit DACs have 6dB SNR improvement and better stability over the single bit quantizer and DACs. The penalty is that the linearity of the feedback DACs should be considered carefully so that the nonlinearity doesn't deteriorate the ADC performance. The tunable delay circuit in the quantizer is designed to adjust the excess loop delay up to +/- 10% to achieve stability and optimal performance

DESIGN OF LOW-POWER LOW-VOLTAGE SUCCESSIVE-APPROXIMATION ANALOG-TO-DIGITAL CONVERTERS

Ph.DDOCTOR OF PHILOSOPH

Design and Implementation of a Novel Flash ADC for Ultra Wide Band Applications

This dissertation presents a design and implementation of a novel flash ADC architecture for ultra wide band applications. The advancement in wireless technology takes us in to a world without wires. Most of the wireless communication systems use digital signal processing to transmit as well as receive the information. The real world signals are analog. Due to the processing complexity of the analog signal, it is converted to digital form so that processing becomes easier. The development in the digital signal processor field is rapid due to the advancement in the integrated circuit technology over the last decade. Therefore, analog-to -digital converter acts as an interface in between analog signal and digital signal processing systems. The continuous speed enhancement of the wireless communication systems brings out huge demands in speed and power specifications of high-speed low-resolution analog-to -digital converters. Even though wired technology is a primary mode of communication, the quality and efficiency of the wireless technology allows us to apply to biomedical applications, in home services and even to radar applications. These applications are highly relying on wireless technology to send and receive information at high speed with great accuracy. Ultra Wideband (UWB) technology is the best method to these applications. A UWB signal has a bandwidth of minimum 500MHz or a fractional bandwidth of 25 percentage of its centre frequency. The two different technology standards that are used in UWB are multiband orthogonal frequency division multiplexing ultra wideband technology (MB-OFDM) and carrier free direct sequence ultra wideband technology (DS-UWB). ADC is the core of any UWB receiver. Generally a high speed flash ADC is used in DS-UWB receiver. Two different flash ADC architectures are proposed in this thesis for DS-UWB applications. The first design is a high speed five bit flash ADC architecture with a sampling rate of 5 GS/s. The design is verified using CADENCE tool with CMOS 90 nm technology. The total power dissipation of the ADC is 8.381 mW from power supply of 1.2 V. The die area of the proposed flash ADC is 186 μm × 210 μm (0.039 mm2). The proposed flash ADC is analysed and compared with other papers in the literature having same resolution and it is concluded that it has the highest speed of operation with medium power dissipation. iii The second design is a reconfigurable five bit flash ADC architecture with a sampling rate of 1.25 GS/s. The design is verified using CADENCE tool with UMC 180 nm technology. The total power dissipation of the ADC is 11.71 mW from power supply of 1.8 V. The die area of the implementation is 432 μm × 720 μm (0.31104 mm2). The chip tape out of the proposed reconfigurable flash ADC is made for fabrication

Design of a low power switched-capacitor pipeline analog-to-digital converter

An Analog to Digital Converter (ADC) is a circuit which converts an analog signal into digital signal. Real world is analog, and the data processed by the computer or by other signal processing systems is digital. Therefore, the need for ADCs is obvious. In this thesis, several novel designs used to improve ADCs operation speed and reduce ADC power consumption are proposed. First, a high speed switched source follower (SSF) sample and hold amplifier without feedthrough penalty is implemented and simulated. The SSF sample and hold amplifier can achieve 6 Bit resolution with sampling rate at 10Gs/s. Second, a novel rail-to-rail time domain comparator used in successive approximation register ADC (SAR ADC) is implemented and simulated. The simulation results show that the proposed SAR ADC can only consume 1.3 muW with a 0.7 V power supply. Finally, a prototype pipeline ADC is implemented and fabricated in an IBM 90nm CMOS process. The proposed design is validated using measurement on a fabricated silicon IC, and the proposed 10-bit ADC achieves a peak signal-to-noise- and-distortion-ratio (SNDR) of 47 dB. This SNDR translates to a figure of merit (FOM) of 2.6N/conversion-step with a 1.2 V power supply

Implementation of Low Power and Area Efficient 2-Bit/Step Asynchronous SAR ADC using Successively Activated Comparators

A low power (0.4-09V) 2-Bit/Step successive approximation register (SAR) analog to digital converter (ADC) is conferred. A 2-Bit/Step operation technique is proposed which implementing a dynamic threshold configuring comparator instead of number of digital to analog converters (DACs). Area and power is reduced by successively activated comparators. Here the second comparator is activated reflecting the preceding comparator’s results. Because the second comparator threshold is configured dynamically for every cycle, only two comparators are required instead of three. By successively activating the comparators, the number of DAC settling is halved, so the power and area overhead is very small and the performance will be increased. The proposed ADC was implemented in a 90nm technology achieved a gain of 35.4 db, power of 0.89 ?w and the conversion time of 0.32ns with a supply voltage of 0.4v. The total core area of this ADC is 7.74 ?m2

A 10-b Fourth-Order Quadrature Bandpass Continuous-Time ΣΔ Modulator With 33-MHz Bandwidth for a Dual-Channel GNSS Receiver

This document is the Accepted Manuscript version of the following article: Junfeng Zhang, Yang Xu, Zehong Zhang, Yichuang Sun, Zhihua Wang, and Baoyong Chi, ‘A 10-b Fourth-Order Quadrature Bandpass Continuous-Time ΣΔ Modulator With 33-MHz Bandwidth for a Dual-Channel GNSS Receiver’, IEEE Transactions on Microwave Theory and Practice, Vol. 65 (4): 1303-1314, first published online 16 February 2017. The version of record is available online at DOI: 10.1109/TMTT.2017.266237, Published by IEEE. © 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.A fourth-order quadrature bandpass continuous-time sigma-delta modulator for a dual-channel global navigation satellite system (GNSS) receiver is presented. With a bandwidth (BW) of 33 MHz, the modulator is able to digitalize the downconverted GNSS signals in two adjacent signal bands simultaneously, realizing dual-channel GNSS reception with one receiver channel instead of two independent receiver channels. To maintain the loop-stability of the high-order architecture, any extra loop phase shifting should be minimized. In the system architecture, a feedback and feedforward hybrid architecture is used to implement the fourth-order loop-filter, and a return-to-zero (RZ) feedback after the discrete-time differential operation is introduced into the input of the final integrator to realize the excess loop delay compensation, saving a spare summing amplifier. In the circuit implementation, power-efficient amplifiers with high-frequency active feedforward and antipole-splitting techniques are employed in the active RC integrators, and self-calibrated comparators are used to implement the low-power 3-b quantizers. These power saving techniques help achieve superior figure of merit for the presented modulator. With a sampling rate of 460 MHz, current-steering digital-analog converters are chosen to guarantee high conversion speed. Implemented in only 180-nm CMOS, the modulator achieves 62.1-dB peak signal to noise and distortion ratio, 64-dB dynamic range, and 59.3-dB image rejection ratio, with a BW of 33 MHz, and consumes 54.4 mW from a 1.8 V power supply.Peer reviewe