Mitigating the Event and Effect of Energy Holes in Multi-hop Wireless Sensor Networks Using an Ultra-Low Power Wake-up Receiver and an Energy Scheduling Technique

This research work presents an algorithm for extending network lifetime in multi-hop wireless sensor networks (WSN). WSNs face energy gap issues around sink nodes due to the transmission of large amounts of data through nearby sensor nodes. The limited power supply to the nodes limits the lifetime of the network, which makes energy efficiency crucial. Multi-hop communication has been proposed as an efficient strategy, but its power consumption remains a research challenge. In this study, an algorithm is developed to mitigate energy holes around the sink nodes by using a modified ultra-low-power wake-up receiver and an energy scheduling technique. Efficient power scheduling reduces the power consumption of the relay node, and when the residual power of the sensor node falls below a defined threshold, the power emitters charge the nodes to eliminate energy-hole problems. The modified wake-up receiver improves sensor sensitivity while staying within the micro-power budget. This study's simulations showed that the developed RF energy harvesting algorithm outperformed previous work, achieving a 30% improvement in average charged energy (AEC), a 0.41% improvement in average energy (AEH), an 8.39% improvement in the number of energy transmitters, an 8.59% improvement in throughput, and a 0.19 decrease in outage probability compared to the existing network lifetime enhancement of multi-hop wireless sensor networks by RF Energy Harvesting algorithm. Overall, the enhanced power efficiency technique significantly improves the performance of WSNs

Analog Signal Buffering and Reconstruction

Wireless sensor networks (WSNs) are capable of a myriad of tasks, from monitoring critical infrastructure such as bridges to monitoring a person\u27s vital signs in biomedical applications. However, their deployment is impractical for many applications due to their limited power budget. Sleep states are one method used to conserve power in resource-constrained systems, but they necessitate a wake-up circuit for detecting unpredictable events. In conventional wake-up-based systems, all information preceding a wake-up event will be forfeited. To avoid this data loss, it is necessary to include a buffer that can record prelude information without sacrificing the power savings garnered by the active use of sleep states.;Unfortunately, traditional memory buffer systems utilize digital electronics which are costly in terms of power. Instead of operating in the target signal\u27s native analog environment, a digital buffer must first expend a great deal of energy to convert the signal into a digital signal. This issue is further compounded by the use of traditional Nyquist sampling which does not adapt to the characteristics of a dynamically changing signal. These characteristics reveal why a digital buffer is not an appropriate choice for a WSN or other resource-constrained system.;This thesis documents the development of an analog pre-processing block that buffers an incoming signal using a new method of sampling. This method requires sampling only local maxima and minima (both amplitude and time), effectively approximating the instantaneous Nyquist rate throughout a time-varying signal. The use of this sampling method along with ultra-low-power analog electronics enables the entire system to operate in the muW power levels. In addition to these power saving techniques, a reconfigurable architecture will be explored as infrastructure for this system. This reconfigurable architecture will also be leveraged to explore wake-up circuits that can be used in parallel with the buffer system

Neuromorphic In-Memory Computing Framework using Memtransistor Cross-bar based Support Vector Machines

This paper presents a novel framework for designing support vector machines (SVMs), which does not impose restriction on the SVM kernel to be positive-definite and allows the user to define memory constraint in terms of fixed template vectors. This makes the framework scalable and enables its implementation for low-power, high-density and memory constrained embedded application. An efficient hardware implementation of the same is also discussed, which utilizes novel low power memtransistor based cross-bar architecture, and is robust to device mismatch and randomness. We used memtransistor measurement data, and showed that the designed SVMs can achieve classification accuracy comparable to traditional SVMs on both synthetic and real-world benchmark datasets. This framework would be beneficial for design of SVM based wake-up systems for internet of things (IoTs) and edge devices where memtransistors can be used to optimize system's energy-efficiency and perform in-memory matrix-vector multiplication (MVM).Comment: 4 pages, 5 figures, MWSCAS 201

Energy-Efficient Wake-up Receivers for 915-MHz ISM Band Applications

Wake-up receiver (WuRx) is a well-known approach for optimizing the latency and power consumption of ultra-low power transceivers in wireless sensor nodes. Tuned RF (TRF) or Envelope Detection architecture is an appropriate topology for short-range Wireless Body Area Network (WBAN) applications, where achieving a very high sensitivity is not a priority. However, the demand for an improved sensitivity gets emphasized for longer transmission ranges. Regardless of the application, considering the existing trade-off between the power and sensitivity, design techniques and novel architectures are usually employed to optimize the power-sensitivity product. Moreover, considering the negative impact of higher data rate on the sensitivity, the energy-sensitivity product can be a more reasonable figure of merit when comparing WuRx designs. In this thesis, the RF-subsampling architecture has been combined with the TRF receiver architecture as a first approach for improving the power-sensitivity product. The overall power consumption is reduced as a result of employing the subsampling topology with a low-frequency local oscillator (LO). Post layout simulations show that the proposed WuRx draws only 56 μA from a 0.5 V supply and exhibits an input sensitivity of -70 dBm for a data rate of 100 kbps. The chip occupies an area of 0.15 mm2 and is fabricated with TSMC 90nm CMOS technology. Another major contribution of this work is to propose and implement a novel dual-mode ultra-low-power WuRx based on the subsampling topology, which not only reduces the overall power consumption but also optimizes the energy-sensitivity product of the receiver. During the typical mode of operation known as the Monitoring (MO) mode, the start frame bits are received at a rate of as low as 10 kbps. Having received the true preamble bits in the MO mode, the remaining wake-up pattern bits are received at a higher rate of 200 kbps during the Identifier (ID) mode. By lowering the gain of the front-end amplifier in the MO mode, the power dissipation is reduced, which in turn causes an increase in the overall noise figure of the receiver. However, adequate sensitivity and hence an optimized energy-sensitivity product is maintained by intentionally lowering the data rate as well as the detection bandwidth of the receiver in the MO mode. The proposed wake-up receiver has been designed and fabricated in IBM 130 nm technology with a core size of about 0.2 mm2 for the target frequency range of 902-928 MHz. The measured results show that the proposed dual-mode receiver achieves a sensitivity of -78.5 dBm and -75 dBm while dissipating an average power of 16.4 µW and 22.9 µW during MO and ID modes, respectively

無線センサネットワークのための超低消費電力と高感度CMOS RF受信機に関する研究

Wireless sensor networks (WSN) have been applied in wide range of applications and proved the more and more important contribution in the modern life. In order to evaluate a WSN, many metrics are considered such as cost, latency, power or quality of service. However, since the sensor nodes are usually deployed in large physical areas and inaccessible locations, the battery change becomes impossible. In this scenario, the power consumption is the most important metric. In a sensor node, the RF receiver is one of the communication devices, which consume a vast majority of power. Therefore, this thesis studies ultra low power RF receivers for the long lifetime of the sensor nodes. Currently, the WSNs use various frequency bands. However, for low power target, the sub-GHz frequency bands are preferred. In this study, ultra-low power 315 MHz and 920 MHz receivers will be proposed for short-range applications and long-range applications of the WSNs respectively. To achieve ultra-low power target, the thesis considers some issues in architecture, circuit design and fabrication technology for suitable choices. After considering different receiver architectures, the RF detection receiver with the On-Off-Keying (OOK) modulation is chosen. Then the thesis proposes solutions to reduce power consumption and concurrently guarantee high sensitivity for the receivers so that they can communicate at adequate distances for both short and long-range applications. First, a 920 MHz OOK receiver is designed for the long-range WSN applications. Typically, the RF amplifiers and local oscillators consume the most of power of RF receivers. In the RF detection receivers, the local oscillators are eliminated, however, the power consumption of the RF amplifiers is still dominant. By reducing the RF gain or removing the RF amplifier, the power consumption of the receivers can be reduced drastically. However, in this case the sensitivity is very limited. In order to overcome the trade-off between power consumption and sensitivity, the switched bias is applied to the RF amplifiers to reduce their power consumption substantially while guaranteeing high RF gain before RF detection. As a result, the receiver consumes only 53 W at 0.6 V supply with -82 dBm sensitivity at 10 kbps data rate. Next, an OOK receiver operating at 315 MHz for the short-range WSN applications with low complexity is proposed. In this receiver, the RF amplifier is controlled to operate intermittently for power reduction. Furthermore, taking advantage of the low carrier frequency, a comparator is used to convert the RF signal to a rail-to-rail stream and then data is demodulated in the digital domain. Therefore, no envelope detector or baseband amplifiers is required. The architecture of the receiver is verified by using discrete RF modules and FPGAs before it is designed on CMOS technology. By simulation with the physical layout, the 315 MHz OOK receiver consumes 27.6 W at 200 kbps and achieves -76.4 dBm sensitivity. Finally, the Synchronized-OOK (S-OOK) modulation scheme is proposed and then an S-OOK receiver operating in the 315 MHz frequency is developed to reduce power consumption more deeply. The S-OOK signal contains not only data but also clock information. By generating a narrow window, the RF front-end is enabled to receive signal only in a short period, therefore, power consumption of the receiver is reduced further. In addition, thank to the clock information contained in the input signal, the data and corresponding clock are demodulated simultaneously without a clock and data recovery circuit. The architecture of the S-OOK receiver is also verified by using discrete RF modules and FPGAs, then VLSI design is carried out. Physical layout simulation shows that the receiver can achieve -76.4 dBm sensitivity, consumes 8.39 W, 4.49 W, 1.36 W at 100 kbps, 50 kbps and 10 kbps respectively. In conclusion, with the objective is to look for solutions to minimize power consumption of receivers for extending the lifetime of sensor nodes while guaranteeing high sensitivity, this study proposed novel receiver architectures, which help reduce power consumption significantly. If using the coin battery CR2032 for power supply, the 920 MHz OOK receiver can work continuously in 1.45 years with communication distance of 259 meters; the 315 MHz OOK receivers can work continuously in 2.8 years with approximately 19 meters communication distance in free space. Whereas, the 315 MHz S-OOK receiver with the minimum power consumption of 1.36 W is suitable for batteryless sensor nodes.電気通信大学201

Small business innovation research. Abstracts of completed 1987 phase 1 projects

Non-proprietary summaries of Phase 1 Small Business Innovation Research (SBIR) projects supported by NASA in the 1987 program year are given. Work in the areas of aeronautical propulsion, aerodynamics, acoustics, aircraft systems, materials and structures, teleoperators and robotics, computer sciences, information systems, spacecraft systems, spacecraft power supplies, spacecraft propulsion, bioastronautics, satellite communication, and space processing are covered

Energy-Efficient Wireless Circuits and Systems for Internet of Things

As the demand of ultra-low power (ULP) systems for internet of thing (IoT) applications has been increasing, large efforts on evolving a new computing class is actively ongoing. The evolution of the new computing class, however, faced challenges due to hard constraints on the RF systems. Significant efforts on reducing power of power-hungry wireless radios have been done. The ULP radios, however, are mostly not standard compliant which poses a challenge to wide spread adoption. Being compliant with the WiFi network protocol can maximize an ULP radio’s potential of utilization, however, this standard demands excessive power consumption of over 10mW, that is hardly compatible with in ULP systems even with heavy duty-cycling. Also, lots of efforts to minimize off-chip components in ULP IoT device have been done, however, still not enough for practical usage without a clean external reference, therefore, this limits scaling on cost and form-factor of the new computer class of IoT applications. This research is motivated by those challenges on the RF systems, and each work focuses on radio designs for IoT applications in various aspects. First, the research covers several endeavors for relieving energy constraints on RF systems by utilizing existing network protocols that eventually meets both low-active power, and widespread adoption. This includes novel approaches on 802.11 communication with articulate iterations on low-power RF systems. The research presents three prototypes as power-efficient WiFi wake-up receivers, which bridges the gap between industry standard radios and ULP IoT radios. The proposed WiFi wake-up receivers operate with low power consumption and remain compatible with the WiFi protocol by using back-channel communication. Back-channel communication embeds a signal into a WiFi compliant transmission changing the firmware in the access point, or more specifically just the data in the payload of the WiFi packet. With a specific sequence of data in the packet, the transmitter can output a signal that mimics a modulation that is more conducive for ULP receivers, such as OOK and FSK. In this work, low power mixer-first receivers, and the first fully integrated ultra-low voltage receiver are presented, that are compatible with WiFi through back-channel communication. Another main contribution of this work is in relieving the integration challenge of IoT devices by removing the need for external, or off-chip crystals and antennas. This enables a small form-factor on the order of mm3-scale, useful for medical research and ubiquitous sensing applications. A crystal-less small form factor fully integrated 60GHz transceiver with on-chip 12-channel frequency reference, and good peak gain dual-mode on-chip antenna is presented.PHDElectrical and Computer EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/162975/1/jaeim_1.pd

Integrated Circuits and Systems for Smart Sensory Applications

Connected intelligent sensing reshapes our society by empowering people with increasing new ways of mutual interactions. As integration technologies keep their scaling roadmap, the horizon of sensory applications is rapidly widening, thanks to myriad light-weight low-power or, in same cases even self-powered, smart devices with high-connectivity capabilities. CMOS integrated circuits technology is the best candidate to supply the required smartness and to pioneer these emerging sensory systems. As a result, new challenges are arising around the design of these integrated circuits and systems for sensory applications in terms of low-power edge computing, power management strategies, low-range wireless communications, integration with sensing devices. In this Special Issue recent advances in application-specific integrated circuits (ASIC) and systems for smart sensory applications in the following five emerging topics: (I) dedicated short-range communications transceivers; (II) digital smart sensors, (III) implantable neural interfaces, (IV) Power Management Strategies in wireless sensor nodes and (V) neuromorphic hardware

Efficient and Interference-Resilient Wireless Connectivity for IoT Applications

With the coming of age of the Internet of Things (IoT), demand on ultra-low power (ULP) and low-cost radios will continue to boost tremendously. The Bluetooth-Low-energy (BLE) standard provides a low power solution to connect IoT nodes with mobile devices, however, the power of maintaining a connection with a reasonable latency remains the limiting factor in defining the lifetime of event-driven BLE devices. BLE radio power consumption is in the milliwatt range and can be duty cycled for average powers around 30μW, but at the expense of long latency. Furthermore, wireless transceivers traditionally perform local oscillator (LO) calibration using an external crystal oscillator (XTAL) that adds significant size and cost to a system. Removing the XTAL enables a true single-chip radio, but an alternate means for calibrating the LO is required. Innovations in both the system architecture and circuits implementation are essential for the design of truly ubiquitous receivers for IoT applications. This research presents two porotypes as back-channel BLE receivers, which have lower power consumption while still being robust in the presents of interference and able to receive back-channel message from BLE compliant transmitters. In addition, the first crystal-less transmitter with symmetric over-the-air clock recovery compliant with the BLE standard using a GFSK-Modulated BLE Packet is presented.PHDElectrical and Computer EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/162942/1/abdulalg_1.pd

Low-Power Wake-Up Receivers

The Internet of Things (IoT) is leading the world to the Internet of Everything (IoE), where things, people, intelligent machines, data and processes will be connected together. The key to enter the era of the IoE lies in enormous sensor nodes being deployed in the massively expanding wireless sensor networks (WSNs). By the year of 2025, more than 42 billion IoT devices will be connected to the Internet. While the future IoE will bring priceless advantages for the life of mankind, one challenge limiting the nowadays IoT from further development is the ongoing power demand with the dramatically growing number of the wireless sensor nodes. To address the power consumption issue, this dissertation is motivated to investigate low-power wake-up receivers (WuRXs) which will significantly enhance the sustainability of the WSNs and the environmental awareness of the IoT. Two proof-of-concept low-power WuRXs with focuses on two different application scenarios have been proposed. The first WuRX, implemented in a cost-effective 180-nm CMOS semiconductor technology, operates at 401−406-MHz band. It is a good candidate for application scenarios, where both a high sensitivity and an ultra-low power consumption are in demand. Concrete use cases are, for instance, medical implantable applications or long-range communications in rural areas. This WuRX does not rely on a further assisting semiconductor technology, such as MEMS which is widely used in state-of-the-art WuRXs operating at similar frequencies. Thus, this WuRX is a promising solution to low-power low-cost IoT. The second WuRX, implemented in a 45-nm RFSOI CMOS technology, was researched for short-range communication applications, where high-density conventional IoT devices should be installed. By investigation of the WuRX for operation at higher frequency band from 5.5 GHz to 7.5 GHz, the nowadays ever more over-traffic issues that arise at low frequency bands such as 2.4 GHz can be substantially addressed. A systematic, analytical research route has been carried out in realization of the proposed WuRXs. The thesis begins with a thorough study of state-of-the-art WuRX architectures. By examining pros and cons of these architectures, two novel architectures are proposed for the WuRXs in accordance with their specific use cases. Thereon, key WuRX parameters are systematically analyzed and optimized; the performance of relevant circuits is modeled and simulated extensively. The knowledge gained through these investigations builds up a solid theoretical basis for the ongoing WuRX designs. Thereafter, the two WuRXs have been analytically researched, developed and optimized to achieve their highest performance. Proof-of-concept circuits for both the WuRXs have been fabricated and comprehensively characterized under laboratory conditions. Finally, measurement results have verified the feasibility of the design concept and the feasibility of both the WuRXs