Analytical Modeling of Nanoscale 4H-SiC MOSFETs for High Power Applications

Threshold voltage instability was investigated for 4H-SiC MOSFETs with SiO2, Si3N4 and HFO2 gate oxides. Threshold voltage changes observed in the drain current Vs. gate voltage (ID-VG) characteristics was determined using various gate voltage sweeps at room temperature. Three types of MOSFETs show different instability characteristics. Depending on gate voltage, many difficulties come up with 4H-SiC MOSFETs, such as low mobility and poor reliability. The characteristics like channel potential, field distribution and the threshold voltage of the proposed models of MOSFETs, 4H-SiC and SOI-4H-SiC were compared with simulator results to validate the models. Short channel effects (SCEs) were also investigated and compared with the existing nanoscale silicon MOSFETs The surface potential model is calculated by using the two-dimensional Poisson equation. The specification of the model are examined by several MOSFET parameters such as body doping concentration, metal gate work function, silicon carbide layer thickness, thickness of metal gate oxide layer, buried oxide thickness, drain to source voltage, and gate to source voltage. The outcomes of modeling and simulation of 4H-SiC MOSFETs model show that the proposed models can reduce short channel effects more than the Silicon MOSFETs. Proposed models highly reduces the drain-induced-barrier-lowering (DIBL) to meet the performance fullfilmant in Nano electronic applications when compared to silicon MOSFETs. Establishing the results, we have noticed that this model can be utilized as a useful tool for the characterization and design of high-efficiency 4H-SiC nanoscale MOSFETs. By matching the two-dimensional device simulation results with analytical modeling, the validity of the recommended models are proven

Study of Silicon Carbide Power MOSFETs Behaviour in Out-of-SOA Conditions

The need for efficient conversion and control of electrical power in many application areas has rapidly increased the demand for power devices with better and better performances. In order to go beyond the limit imposed by Silicon devices, there has always been a great interest for new materials. In recent years, Silicon Carbide Power devices, mainly power diodes and MOSFETs, have become commercially available and have begun to replace their Silicon counterpart in many application areas. The reason lays in some superior material properties that allow developing higher efficient power systems. Nevertheless, a wider spread of these devices could not be achieved without a deep analysis of the elements that might affect their reliability. The current work deals with the study of SiC Power MOSFETs reliability, with particular focus on short-circuit operation. To achieve this purpose, wide set of experiments has been carried out on commercially available devices, providing both electrical and thermal characterization. Alongside experimental evidences, TCAD simulations have been used to get a full understanding of the inner physical failure dynamics. Eventually, it has been possible to give explanation about SiC Power MOSFETs failure mechanisms. In particular, two different phenomena might occur and both are related to temperature increase inside the device

Miniaturized Transistors, Volume II

In this book, we aim to address the ever-advancing progress in microelectronic device scaling. Complementary Metal-Oxide-Semiconductor (CMOS) devices continue to endure miniaturization, irrespective of the seeming physical limitations, helped by advancing fabrication techniques. We observe that miniaturization does not always refer to the latest technology node for digital transistors. Rather, by applying novel materials and device geometries, a significant reduction in the size of microelectronic devices for a broad set of applications can be achieved. The achievements made in the scaling of devices for applications beyond digital logic (e.g., high power, optoelectronics, and sensors) are taking the forefront in microelectronic miniaturization. Furthermore, all these achievements are assisted by improvements in the simulation and modeling of the involved materials and device structures. In particular, process and device technology computer-aided design (TCAD) has become indispensable in the design cycle of novel devices and technologies. It is our sincere hope that the results provided in this Special Issue prove useful to scientists and engineers who find themselves at the forefront of this rapidly evolving and broadening field. Now, more than ever, it is essential to look for solutions to find the next disrupting technologies which will allow for transistor miniaturization well beyond silicon’s physical limits and the current state-of-the-art. This requires a broad attack, including studies of novel and innovative designs as well as emerging materials which are becoming more application-specific than ever before

Characterization and Modeling of Semiconductor Power Devices Reliability

This thesis aims at studying, characterizing and modeling the trapping and de-trapping mechanisms occurring during the ON-state operation mode and leading to the degradation of semiconductor power devices. In this operating condition, the combined effect of moderate electric fields, high currents and temperatures due to self-heating effects can seriously affect the long-term reliability leading to device failure. Detailed analyses are performed on both silicon and gallium nitride based technologies by means of accelerated life test methods and electro-thermal simulations, aimed at understanding the physical origins of the degradation. In particular, this thesis provides the following contributions: i) the role of the interface and oxide trapped charge induced by negative bias temperature instability (NBTI) stress in p-channel Si-based U-MOSFETs is investigated. The impact of relevant electrical and physical parameters, such as stress voltage, recovery voltage and temperature, is accounted for and proper models are also proposed. In the field of innovative semiconductor power devices, this work focuses on the study of GaN-based devices. In particular, three different subtopics are considered: ii) a thermal model, accounting for the temperature dependence of the thermal boundary resistance (TBR), is implemented in TCAD simulator in order to realistically model self-heating effects in GaN-based power devices; iii) the degradation mechanisms induced by ON-state stress in GaN-based Schottky barrier diodes (SBDs) are proposed by analyzing their dependence on the device geometry; iv) the trapping mechanisms underlying the time-dependent gate breakdown and their effects on the performance of GaN-based power HEMTs with p-type gate are investigated, and an original empirical model representing the relationship between gate leakage current and time to failure is proposed

Measurements and review of failure mechanisms and reliability constraints of 4H-SiC Power MOSFETs under short circuit events

The reliability of the SiC MOSFET has always been a factor hindering the device application, especially under high voltage and high current conditions, such as in the short circuit events. This paper experimentally reviews the failure mechanisms caused by destructive short circuit impulses, and investigates the degradation patterns of key electrical parameters under repetitive short circuit events. The impact of test parameters on the short circuit reliability of SiC MOSFET has been analyzed. Approaches to characterize the electrical-thermal-mechanical stress during the short circuit period and advanced test methods are highlighted. Finally, the constraints from the standpoint of both manufacturers and users have been presented, including comparison of current SiC MOSFET devices, reliability evaluation of parallel SiC MOSFET devices, reliability improvement of the chip, performance improvement of protection circuits, and reliability assessment of SiC MOSFET devices under application-representative stress

IMPEDANCE SPECTROSCOPY FOR INTERFACE CHARACTERIZATION IN SEMICONDUCTOR DEVICES

Impedance spectroscopy (IS) is a powerful tool to characterize devices since it allows to easily decouple the contribution of different interfaces existing in the device by only accessing the external terminals. The collected data are interpreted by means of equivalent electrical circuit. In this thesis, an automated procedure is developed to automatically extract lumped circuit parameters from impedance measured data, adding physical constraints deriving from experimental capacitance. In this work, Graphene-Silicon solar cells are characterized using impedance spectra, allowing to assess a new front contact technology that ameliorates these cells performance compared to the conventional. Impedance spectroscopy is also employed to characterize perovskite solar cells. The equivalent circuit coming from these devices allows to gain knowledge on perovskite layer and recombination mechanisms. An important focus of this thesis concerns capacitance versus voltage curves in forward bias region. This analysis is made using both experimental data and numerical results obtained from TCAD environment. This study is made on Metal-Semiconductor structure, finding the analytical expression of the forward bias capacitance peak and considering the effects of interface defects on capacitance behavior. The observation of multiple peaks arising in the high forward bias region suggests that interface properties are not uniform in the entire structure. Capacitance is also investigated in SiC MOSFETs devices permitting the TCAD model calibration and SiC/SiO2 interface characterization

Benchmarking the robustness performance of SiC cascode JFETS against contemporary devices using simulations and experimental measurements

This thesis provides the first comprehensive benchmarking exercise of SiC Cascode JFETs against similarly rated SiC Planar MOSFETs, Trench MOSFETs and other devices. Experimental measurements of short circuits in single and parallel devices, single and repetitive unclamped inductive switching as well as double pulse tests are used together with finite element simulations throughout the thesis. Power device robustness measures how well a device can sustain shocks during anomalous operation. These operating conditions are high voltages that exceed the device breakdown (avalanche conduction), or simultaneous high current and voltage through the device (Short circuit conduction). The silicon Carbide (SiC) cascode JFET is an electronic switch that combines two power devices, a low voltage silicon (Si) MOSFET and a high voltage SiC JFET operating as a single switch. This configuration avoids the challenges of reduced gate oxide reliability in SiC MOSFETs, and negative turn-on Voltage for JFETs. However, the robustness of SiC cascode JFETs have not been examined as extensively as conventional devices. Hence, this thesis investigates the robustness of SiC cascode JFETs as well as the failure modes during such operation and benchmarks the performance against conventional devices. Analysis of avalanche robustness in SiC Cascode JFETs indicated a peculiar style of failure at high temperatures characterised by a soft failure (delayed turn-off, change of current slope, and dip in voltage), and an eventual catastrophic failure. This failure is different from other devices analysed which demonstrated a single catastrophic failure. The results show that the gate resistance of the SiC JFET plays a crucial role during avalanche mode conduction. Finite element simulations confirm this observation. The Short circuit (SC) robustness analysis of the SiC Cascode JFET demonstrated invariability with temperature. In contrast, benchmarked devices show a SC correlation with temperature. The short circuit operation also revealed the Cascode JFET fails with a drain source short while the gate-source junction is still functional. Also revealed is the crucial role of increasing JFET gate resistance in reducing short circuit robustness. The SC robustness is also analysed for parallel connected devices. The analysis demonstrates the parameters with the largest impact on SC current shared between paralleled devices. Variation in the embedded JFET gate resistance within the cascode JFET presents with the highest impact as confirmed by finite element simulation, while interface charges and the doping of the CSL region present with the largest impact in SiC MOSFET

Plasmonic Terahertz Detector Based on Asymmetric Silicon Field-Effect Transistor for Real-Time Terahertz Imaging System

Department of Electrical EngineeringTerahertz (THz) technology has a great potential application owing to the unique properties of THz wave that has both permeability and feature of straight. Among the various technology in THz frequency range, THz imaging technology is very promising and attractive owing to harmlessness in human body by very low energy. In particular, for real-time THz imaging detectors, field-effect transistor (FET)-based THz detectors are now being intensively developed in multi-pixel array configuration by exploiting the silicon (Si) technology advantages of low-cost and high density integration. FET-based plasmonic wave detection mechanism, which is not limited by cut-off frequency as in transit-mode, has attractive features such as enhanced responsivity (Rv) according to frequency increase in THz range and robustness to high THz input power. To analyze the operation principle of plasmonic THz detector, an analytical device model has been implemented in terms of device physics. The non-resonant and ???overdamped??? plasma-wave behaviors have been modeled by introducing a quasi-plasma electron charge box as a two-dimensional electron gas (2DEG) in the channel region only around the source side of Si FETs. Based on the coupled non-resonant plasma-wave physics and continuity equation on the technology computer-aided design (TCAD) platform, the alternate-current (ac) signal as an incoming THz wave radiation successfully induced a direct-current (dc) drain-to-source output voltage as a detection signal in a sub-THz frequency regime under the asymmetric boundary conditions between source and drain. The significant effects of asymmetric source and drain structure, channel shape on the charge asymmetry and performance enhancement have been analytically investigated based on non-resonant plasmonic THz detection theory. By designing and fabricating an asymmetric transistor integrated with antenna, more enhanced channel charge asymmetry has been obtained for enhanced detection response. Through verification of the advanced non-quasi-static (NQS) compact model, the intrinsic FET delay and total detector delay in THz plasmonic detection are successfully characterized and are small enough to guarantee a real-time operating detector. These results can provide that the real-time THz imaging of moving objects has been experimentally demonstrated based on plasmonic 1x200 array scanner by using the high/fast detecting performance asymmetric FET and multiplexer/amplifier circuits. The highly-enhanced Rv and reduced noise equivalent power (NEP) have been demonstrated by exploiting monolithic transistor-antenna device considering impedance matching between transistor and antenna. This record-high enhancement is due to antenna mismatching and feeding line loss reduction as well as the enhanced charge asymmetry in the proposed monolithic transistor-antenna device. Therefore, high-performance plasmonic THz detector based on asymmetric Si FET can compete as commercial THz detector by taking advantages of monolithic device technology for real-time THz imaging system.ope

Reliability analysis of planar and symmetrical & asymmetrical trench discrete SiC Power MOSFETs

Silicon Carbide MOSFETs are shown in research to outperform Silicon counterparts on many performance metrics, including switching rates and power losses. To further improve their performance, trench and double-trench structures have recently been developed. To replace conventional planar SiC MOSFETs, besides the performance parameters which are mostly stated in datasheets, reliability studies under stress are also needed. This thesis presents a comprehensive comparison between 3rd generation trench SiC power MOSFETs, namely symmetrical double-trench and asymmetrical trench with planar SiC power MOSFETs on four aspects of: switching slew rates (dI/dt & dV/dt), crosstalk characteristics, bias temperature instability and power cycling stability.First, the dynamic performance in both 1st quadrant and 3rd quadrant has been eval- uated on the differences in stress by dI/dt & dV/dt and resultant losses. This is key in understanding many other reliability criterions, i.e. severity of crosstalk induced switchings. In the 1st quadrant, the source current and drain-source voltage switching rates at both turn-ON and turn-OFF are measured under a range of test conditions. Both the symmetrical and asymmetrical trench MOSFETs have up to 2 times faster voltage and current slew rates compared with the planar one. They also indicate only slight changes in switching rate with junction temperature. In the 3rd quadrant, the reverse recovery peak current and total reverse recovery charge are measured with respect to junction temper- ature and load current level. Both the symmetrical and asymmetrical trench MOSFETs have less than half of the reverse recovery charge of that of the planar SiC MOSFET.In the evaluation of crosstalk characteristics, peak shoot-through current and induced gate voltage at crosstalk are measured with respect to junction temperature and external gate resistance. With particularly large external gate resistances connected to intentionally induce parasitic turn-ON, the symmetrical double-trench MOSFET is shown to be more prone to crosstalk with 23 A peak shoot-through current measured while it is only 10 A for asymmetrical trench and 4 A for planar MOSFET under similar test conditions. As the temperature increase, the peak shoot-through current drops for the symmetrical double-trench, while constant for the asymmetrical trench and rising for the planar device.Threshold voltage drift is also measured to reflect the degradation happened with bias temperature instability at various junction temperatures, stressing voltages and time periods. Under low-magnitude gate stress (within the range of datasheets) in both positive and negative bias cases, there is more threshold drift observed on the two trench MOSFETs at all junction temperatures than the planar MOSFET. When the stress magnitude is raised, there is less threshold drift observed on the two trench MOSFETs.To evaluate the ruggedness in continuous switchings, the devices are placed under repetitive turn-ON events. The thermal performance under such operation are compared. The asymmetrical trench MOSFET experiences the highest case temperature rise while the least is observed for the planar MOSFET. With an external heatsink equipped to achieve more efficient cooling, the repetitive turn-ON test transforms into the conventional power cycling. In this condition, both the symmetrical and asymmetrical trench MOSFETs fail earlier than the degraded (but not failed) planar MOSFET

Strain-Engineered MOSFETs

This book brings together new developments in the area of strain-engineered MOSFETs using high-mibility substrates such as SIGe, strained-Si, germanium-on-insulator and III-V semiconductors into a single text which will cover the materials aspects, principles, and design of advanced devices, their fabrication and applications. The book presents a full TCAD methodology for strain-engineering in Si CMOS technology involving data flow from process simulation to systematic process variability simulation and generation of SPICE process compact models for manufacturing for yield optimization