Photonic packaging: transforming silicon photonic integrated circuits into photonic devices

Dedicated multi-project wafer (MPW) runs for photonic integrated circuits (PICs) from Si foundries mean that researchers and small-to-medium enterprises (SMEs) can now afford to design and fabricate Si photonic chips. While these bare Si-PICs are adequate for testing new device and circuit designs on a probe-station, they cannot be developed into prototype devices, or tested outside of the laboratory, without first packaging them into a durable module. Photonic packaging of PICs is significantly more challenging, and currently orders of magnitude more expensive, than electronic packaging, because it calls for robust micron-level alignment of optical components, precise real-time temperature control, and often a high degree of vertical and horizontal electrical integration. Photonic packaging is perhaps the most significant bottleneck in the development of commercially relevant integrated photonic devices. This article describes how the key optical, electrical, and thermal requirements of Si-PIC packaging can be met, and what further progress is needed before industrial scale-up can be achieved

A novel laser diode wavelength stabilisation technique for use in high resolution spectroscopy

Tuneable diode laser absorption spectroscopy (TDLAS) based gas sensors are widely used for trace gas detection for their high selectivity and sensitivity. The laser source used in TDLAS requires a narrow line width in the order of 10s of MHz, with a wavelength stability multiple orders lower than the molecular absorption line width, which is, for example, 4.1GHz (38pm) for an air broadened methane line. TDLAS requires the use of a laser diode with a long term wavelength stability of better than 10% of the absorption line width of the target gas species. The wavelength stability of the laser is highly temperature dependent as the wavelength increases with increasing temperature. Therefore, control of the temperature of the laser diode is vital for stabilising the laser emission wavelength. In this thesis, a novel method has been proposed to measure and stabilise the temperature of a laser diode. The laser diode emission wavelength was stabilised by using its measured junction voltage in a control feedback loop. In order to determine the junction voltage, a series resistance correction term was identified, which was the novel part of this wavelength stabilisation technique. The laser diode junction and forward voltages were calculated from the forward voltage drop of the laser diode at measured at various operating temperatures. The laser diode series resistance was measured dynamically and was subtracted from the forward voltage to calculate the junction voltage. Both the forward voltage and series resistances were found to be temperature dependent. This method was investigated for its short term (~ 5minute) and long term (~ 1 hour) wavelength stability and was compared with other available methods. The laser diode wavelength stability attained using this method has been also investigated at various ambient temperatures (10-40 °C). ...[cont.

Novel optical transmitters for high speed optical networks

The objective of this thesis is to investigate the performance of novel optical transmitter lasers for use in high speed optical networks. The laser technology considered is the discrete mode laser diode (DMLD) which is designed to achieve single wavelength operation by etching features on the surface of the ridge waveguide. This leads to a simplified manufacturing process by eliminating the regrowth step used in conventional approaches, presenting an economic approach to high volume manufacture of semiconductor lasers. Two application areas are investigated in this work. The bit rate in next generation access networks is moving to 10 Gbit/s. This work characterises the performance of DMLDs designed for high speed operation with the objective of identifying the limitations and improving performance to meet the specifications for uncooled operation at 10 Gbit/s. With the deployment of advanced modulation formats the phase noise of the laser source has become an important parameter, particularly for higher order formats. DMLDs were developed for narrow linewidth operation. The linewidth of these devices was characterised and a value as low as 70 kHz was demonstrated. Transmission experiments were also carried out using a coherent transmission test bed and the performance achieve is compared with that of an external cavity laser

Proceedings of the 1977 NASA/ISHM Microelectronics Conference

Current and future requirements for research, development, manufacturing and education in the field of hybrid microelectronic technology were discussed

Otimização de soluções de fotónica integrada para sistemas óticos de nova geração

Next generation optical systems can highly benefit from optimized photonic integrated solutions. Photonic integrated circuits (PIC) appear as a promising technology under the current demand for flexibility/reconfigurability in optical systems and telecommunications networks. PIC-based optical systems offer an efficient and cost-effective solution to data transmission increasing claims. In order to contribute to the development of integrated photonic technology, optimized PIC solutions addressing different steps of the PIC development chain, mainly design, testing, and packaging processes, are investigated. Optical signal data compression techniques are progressing to sustain the fast processing/storing of large amounts of bandwidth demanding data, with the advantage of resorting to photonic integrated solutions for the implementation of optical transforms, e.g., Haar transform (HT). This demand motivated the research of an optimized PIC design solution in silicon nitride (Si3N4) based platform comprising a two-level HT network for compression, and a switching network as a framework that supplies all logical inputs of the HT network for testing/characterization purposes. Optimized design models for the multimode interference key building block structure of the PIC design solution, are proposed. Additionally, a first test and characterization of PIC solutions implementing the HT for compression applications in indium phosphide (InP) based platform and in a new organic-inorganic hybrid material were realized. Taking advantage of a tunable lattice filter dispersion compensator in Si3N4-based integrated platform, it was demonstrated a real-time extended reach PAM-4 transmission over 40 km enabled by the photonic integrated dispersion compensator, with application in data center interconnects. Under photonic integrated high-Q resonators need for accurate performance measurement, a technique based on RF calibrated Mach-Zehnder interferometer, and Brillouin gain measurements through Lorentzian fitting analysis were successfully attained. Finally, as technical and functional requirements of PIC demand a thorough characterization/testing to provide an accurate prediction of its performance, and current testing platforms can be expensive and have low flexibility, a proof of concept of a new soft-packaging flexible platform for photonic integrated processors and spatial division multiplexing systems, based in spatial light modulation operation principle is proposed.Os sistemas óticos de nova geração beneficiam com a otimização de fotónica integrada. Com os circuitos de fotónica integrada (PIC) avançados a surgir como uma tecnologia promissora, dentro da crescente procura por flexibilidade/ reconfigurabilidade dos sistemas óticos e redes de telecomunicações. Os sistemas óticos baseados em PIC oferecem soluções eficientes e rentáveis em resposta às necessidades crescentes de transmissão de dados. De modo a contribuir para o desenvolvimento tecnológico associado à fotónica integrada, são investigados no âmbito desta dissertação diferentes soluções otimizadas de PIC, abordando diferentes estágios do seu desenvolvimento, nomeadamente projeto/design, teste e encapsulamento. Técnicas de compressão de sinais óticos estão a progredir no sentido de apoiar a expansão de velocidade de processamento e quantidade de armazenamento com elevada largura de banda associada. São esperadas vantagens recorrendo a PIC para a implementação de transformadas óticas, e.g., transformada de Haar (HT). Esta necessidade motivou a investigação de soluções de PIC com design otimizado, desenvolvidas em plataforma integrada de nitreto de silício (Si3N4). O PIC desenhado é constituído por uma rede 2D a executar a HT para fins de compressão e uma rede de comutação para produzir todas as entradas lógicas esperadas para teste e caracterização. São propostos modelos de design otimizados para a estrutura elementar que compõe o PIC, i.e., componente de interferência multimodal. Adicionalmente, foi realizado o primeiro teste e caracterização experimental de um PIC implementando a HT para fins de compressão, numa plataforma integrada de fosfato de índio (InP) e num material orgânico-inorgânico híbrido. Tirando partido de um filtro sintonizável para compensação de dispersão, desenvolvido em plataforma integrada de Si3N4, foi demostrado um link de transmissão alargada (40 km) em modulação PAM-4, com possível aplicação em centros de processamento de dados de interconexão. A necessidade de medições precisas de desempenho para a caracterização efetiva de soluções integradas de ressoadores de elevado fator de qualidade, motivou a implementação de uma técnica de medição eficaz. Esta é baseada num interferómetro de Mach-Zehnder calibrado em rádio frequência e na realização de mediações de ganho de Brillouin por análise Lorentziana de ajuste de curva. Por fim, tendo em conta os rigorosos requisitos técnicos e funcionais associados ao teste/caracterização precisa de PIC e o facto de as atuais soluções serem dispendiosas e pouco flexíveis. Uma prova de conceito de uma nova plataforma flexível de encapsulamento por software é proposta com aplicação em processadores PIC e sistemas com multiplexagem por divisão espacial.Programa Doutoral em Telecomunicaçõe

Addressing Fiber-to-Chip Coupling Issues in Silicon Photonics

Esta tesis trata de resolver el problema de la interconexión (acoplo) entre un circuito integrado fotónico de silicio (chip) y el mundo exterior, es decir una fibra óptica. Se trata de uno de los temas más importantes a los que hoy en día se enfrenta la comunidad científica en óptica integrada de silicio. A pesar de que pueden realizarse circuitos integrados fotónicos de silicio de muy alta calidad utilizando herramientas estándar de fabricación CMOS, la interfaz con la fibra óptica sigue siendo la fuente más importante de pérdidas, debido a la gran diferencia en el tamaño entre los modos de propagación de la fibra y de las guías de los circuitos integrados fotónicos. Abordar el problema es, por lo tanto, muy importante para poder utilizar los circuitos integrados fotónicos de silicio en una aplicación práctica. Objetivos: El propósito de este trabajo es hacer frente a este problema en la interfaz del acoplamiento fibra-chip, con énfasis en el ensamblado o empaquetado final. Por lo tanto, los objetivos principales son: 1) estudio, modelado y optimización de diseños de diferentes técnicas eficientes de acoplamiento entre fibras ópticas y circuitos integrados fotónicos de silicio, 2) fabricación y demostración experimental de los diseños obtenidos, 3) ensamblado y empaquetado de algunos de los prototipos de acoplamiento fabricados. Metodología: Este trabajo se desarrolla a lo largo de dos líneas de investigación, en conformidad con las dos principales estrategias de acoplamiento que pueden encontrarse en la literatura, concretamente, estructuras de acoplamiento tipo "grating" (la fibra acopla verticalmente sobre la superficie de circuito), y estructuras del tipo ¿inverted taper¿ (la fibra acopla horizontalmente por el extremo de circuito). Resultados: tanto en el caso de estructuras tipo "grating" como en el caso de estructuras "inverted taper", son importantes los avances conseguidos sobre el estado del arte. En lo que respecta al "grating", se ha demostrado dos tipos de estructuras. Por un lado, se ha demostrado "gratings" adecuados para acoplo a guías de silicio convencionales. Por otra parte, se ha demostrado por primera vez el funcionamiento de "gratings" para guías de silicio tipo "slot" horizontal, que son un tipo de guía muy prometedora para aplicaciones de óptica no lineal. En relación con el acoplamiento a través de "inverted taper", se ha demostrado una estructura novedosa basada en este tipo de acoplamiento. Con esta estructura, importantes son los avances conseguidos en el empaquetado de fibras ópticas con el circuito de silicio. Su innovadora integración con estructuras de tipo "V-groove" se presenta como un medio para alinear pasivamente conjuntos de múltiples fibras a un mismo circuito integrado fotónico. También, se estudia el empaquetado de conjuntos de múltiples fibras usando acopladores tipo "grating", resultando en un prototipo de empaquetado de reducido tamaño.Galán Conejos, JV. (2010). Addressing Fiber-to-Chip Coupling Issues in Silicon Photonics [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/9196Palanci

High speed photodiode and 90° optical hybrid for 2 µm optical communication systems

In order to maximize the capacity using these C-band wavelengths, more and more efforts have to be exerted by the equipment providers to increase capacity and suppress cross talk between adjacent channels. To overcome this capacity saturation around 1.55 µm, the next generation optical networks require technological developments in new wavelength regions. This will not only extend the current effective transmission band but also address limitations such as loss and non-linearity of silica-core fibers. The waveband at 2 µm can be recognized as a potential candidate due to the low loss window in Hollow Core Photonic Band Gap Fibers (HCPBGF) and the gain bandwidth from Thulium Doped Fiber Amplifier (TDFA). Furthermore this waveband can take advantage of the previous research and development ideas based on 1.55 µm while extending the technologies related to materials and processing for the passive and active components. To satisfy the system-level applications at this new wave band, opto-electronics devices at 2 µm should be developed. In this thesis, we present the building blocks regarding material optimization, device design, process development and performance characterizations of high speed photodiodes and associated 90° optical hybrids at 2 µm. All types of the photodiode devices have been packaged with the support from the package group for high speed test to prove the ability to work in the real optical communication system. For the optical 90° hybrids, design of large spot size diluted waveguide, dimension optimization of 4×4 Multiple Mode Interference (MMI) coupler, and monolithic integration test structure involving hybrid and Mach-Zehnder Interferometer (MZI) are achieved. The devices have displayed the potential to be applied in real 2 µm optical communication systems while the photodiode is also useful in gas sensing area such as carbon dioxide mapping of the atmosphere on the earth

Cross-Layer Pathfinding for Off-Chip Interconnects

Off-chip interconnects for integrated circuits (ICs) today induce a diverse design space, spanning many different applications that require transmission of data at various bandwidths, latencies and link lengths. Off-chip interconnect design solutions are also variously sensitive to system performance, power and cost metrics, while also having a strong impact on these metrics. The costs associated with off-chip interconnects include die area, package (PKG) and printed circuit board (PCB) area, technology and bill of materials (BOM). Choices made regarding off-chip interconnects are fundamental to product definition, architecture, design implementation and technology enablement. Given their cross-layer impact, it is imperative that a cross-layer approach be employed to architect and analyze off-chip interconnects up front, so that a top-down design flow can comprehend the cross-layer impacts and correctly assess the system performance, power and cost tradeoffs for off-chip interconnects. Chip architects are not exposed to all the tradeoffs at the physical and circuit implementation or technology layers, and often lack the tools to accurately assess off-chip interconnects. Furthermore, the collaterals needed for a detailed analysis are often lacking when the chip is architected; these include circuit design and layout, PKG and PCB layout, and physical floorplan and implementation. To address the need for a framework that enables architects to assess the system-level impact of off-chip interconnects, this thesis presents power-area-timing (PAT) models for off-chip interconnects, optimization and planning tools with the appropriate abstraction using these PAT models, and die/PKG/PCB co-design methods that help expose the off-chip interconnect cross-layer metrics to the die/PKG/PCB design flows. Together, these models, tools and methods enable cross-layer optimization that allows for a top-down definition and exploration of the design space and helps converge on the correct off-chip interconnect implementation and technology choice. The tools presented cover off-chip memory interfaces for mobile and server products, silicon photonic interfaces, 2.5D silicon interposers and 3D through-silicon vias (TSVs). The goal of the cross-layer framework is to assess the key metrics of the interconnect (such as timing, latency, active/idle/sleep power, and area/cost) at an appropriate level of abstraction by being able to do this across layers of the design flow. In additional to signal interconnect, this thesis also explores the need for such cross-layer pathfinding for power distribution networks (PDN), where the system-on-chip (SoC) floorplan and pinmap must be optimized before the collateral layouts for PDN analysis are ready. Altogether, the developed cross-layer pathfinding methodology for off-chip interconnects enables more rapid and thorough exploration of a vast design space of off-chip parallel and serial links, inter-die and inter-chiplet links and silicon photonics. Such exploration will pave the way for off-chip interconnect technology enablement that is optimized for system needs. The basis of the framework can be extended to cover other interconnect technology as well, since it fundamentally relates to system-level metrics that are common to all off-chip interconnects