2,882 research outputs found
Smart Sensor Networks For Sensor-Neural Interface
One in every fifty Americans suffers from paralysis, and approximately 23% of paralysis cases are caused by spinal cord injury. To help the spinal cord injured gain functionality of their paralyzed or lost body parts, a sensor-neural-actuator system is commonly used. The system includes: 1) sensor nodes, 2) a central control unit, 3) the neural-computer interface and 4) actuators. This thesis focuses on a sensor-neural interface and presents the research related to circuits for the sensor-neural interface.
In Chapter 2, three sensor designs are discussed, including a compressive sampling image sensor, an optical force sensor and a passive scattering force sensor. Chapter 3 discusses the design of the analog front-end circuit for the wireless sensor network system. A low-noise low-power analog front-end circuit in 0.5ÎŒm CMOS technology, a 12-bit 1MS/s successive approximation register (SAR) analog-to-digital converter (ADC) in 0.18ÎŒm CMOS process and a 6-bit asynchronous level-crossing ADC realized in 0.18ÎŒm CMOS process are presented. Chapter 4 shows the design of a low-power impulse-radio ultra-wide-band (IR-UWB) transceiver (TRx) that operates at a data rate of up to 10Mbps, with a power consumption of 4.9pJ/bit transmitted for the transmitter and 1.12nJ/bit received for the receiver. In Chapter 5, a wireless fully event-driven electrogoniometer is presented. The electrogoniometer is implemented using a pair of ultra-wide band (UWB) wireless smart sensor nodes interfacing with low power 3-axis accelerometers. The two smart sensor nodes are configured into a master node and a slave node, respectively. An experimental scenario data analysis shows higher than 90% reduction of the total data throughput using the proposed fully event-driven electrogoniometer to measure joint angle movements when compared with a synchronous Nyquist-rate sampling system.
The main contribution of this thesis includes: 1) the sensor designs that emphasize power efficiency and data throughput efficiency; 2) the fully event-driven wireless sensor network system design that minimizes data throughput and optimizes power consumption
Low power 9-bit 500 kS/s 2-stage cyclic ADC using OTA variable bias current
This paper presents a 9-bit, 2-stage cyclic analog to digital converter (ADC) with a variable bias current control circuitry to reduce its power dissipation. Each stage outputs a three-bit digital word and the circuit requires four subcycles to perform a whole conversion. Since the accuracy required is higher in the first stage and first subcycle and decreases in subsequent cycles, the bias current of each operational transconductance amplifier is regulated depending on the subcycle of the conversion process. The resolution and sampling frequency of the converter make it suitable to be integrated with 8-bit CMOS imagers with column-parallel ADC architectures. The ADC has been designed using a 1.2âV 110ânm CMOS technology and the circuit consumes 27.9â”W at a sampling rate of 500 kS/s. At this sampling rate and at a 32âkHz input frequency, the circuit achieves 56âdB of SNDR and 9 bit ENOB. The Figure of Merit is 109 fJ/step.This work has been partially funded by Spanish Ministerio de Ciencia e InnovaciĂłn (MCI), Agencia Estatal de InvestigaciĂłn (AEI) and European Region Development Fund (ERDF/FEDER) under grant RTI2018-097088-B-C3
Integration of an imaging system and A/D converter system
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1997.Includes bibliographical references (p. 25).by Jasen C. Li.M.Eng
A review of advances in pixel detectors for experiments with high rate and radiation
The Large Hadron Collider (LHC) experiments ATLAS and CMS have established
hybrid pixel detectors as the instrument of choice for particle tracking and
vertexing in high rate and radiation environments, as they operate close to the
LHC interaction points. With the High Luminosity-LHC upgrade now in sight, for
which the tracking detectors will be completely replaced, new generations of
pixel detectors are being devised. They have to address enormous challenges in
terms of data throughput and radiation levels, ionizing and non-ionizing, that
harm the sensing and readout parts of pixel detectors alike. Advances in
microelectronics and microprocessing technologies now enable large scale
detector designs with unprecedented performance in measurement precision (space
and time), radiation hard sensors and readout chips, hybridization techniques,
lightweight supports, and fully monolithic approaches to meet these challenges.
This paper reviews the world-wide effort on these developments.Comment: 84 pages with 46 figures. Review article.For submission to Rep. Prog.
Phy
Low-Noise Energy-Efficient Sensor Interface Circuits
Today, the Internet of Things (IoT) refers to a concept of connecting any devices on network where environmental data around us is collected by sensors and shared across platforms. The IoT devices often have small form factors and limited battery capacity; they call for low-power, low-noise sensor interface circuits to achieve high resolution and long battery life. This dissertation focuses on CMOS sensor interface circuit techniques for a MEMS capacitive pressure sensor, thermopile array, and capacitive microphone.
Ambient pressure is measured in the form of capacitance. This work propose two capacitance-to-digital converters (CDC): a dual-slope CDC employs an energy efficient charge subtraction and dual comparator scheme; an incremental zoom-in CDC largely reduces oversampling ratio by using 9b zoom-in SAR, significantly improving conversion energy.
An infrared gesture recognition system-on-chip is then proposed. A hand emits infrared radiation, and it forms an image on a thermopile array. The signal is amplified by a low-noise instrumentation chopper amplifier, filtered by a low-power 30Hz LPF to remove out-band noise including the chopper frequency and its harmonics, and digitized by an ADC. Finally, a motion history image based DSP analyzes the waveform to detect specific hand gestures.
Lastly, a microphone preamplifier represents one key challenge in enabling voice interfaces, which are expected to play a dominant role in future IoT devices. A newly proposed switched-bias preamplifier uses switched-MOSFET to reduce 1/f noise inherently.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/137061/1/chaseoh_1.pd
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Fully-passive switched-capacitor techniques for high performance SAR ADC design
In recent years, SAR ADC becomes more and more popular in various low-power applications such as wireless sensors and low energy radios due to its circuit simplicity, high power efficiency, and scaling compatibility. However, its speed is limited by its successive approximation procedures and its power efficiency greatly reduces with the ADC resolution going beyond 10 bit. To address these issues, this thesis proposes to embed two techniques: 1) compressive sensing (CS) and 2) noise shaping (NS) to a conventional SAR ADC. The realization of both techniques are based on fully-passive switched-capacitor techniques.
CS is a recently emerging sampling paradigm, stating that the sparsity of a signal can be exploited to reduce the ADC sampling rate below the Nyquist rate. Different from conventional CS frameworks which require dedicated analog CS encoders, this thesis proposes a fully-passive CS-SAR ADC architecture which only requires minor modification to a conventional SAR ADC. Two chips are fabricated in a 0.13 ”m process to prove the concept. One chip is a single-channel CS-SAR ADC which can reduce the ADC conversion rate by 4 times, thus reducing the ADC power by 4 times. In many wireless sensing applications, multiple ADCs are commonly required to sense multi-channel signals such as multi-lead ECG sensing and parallel neural recording. Therefore, the other chip is a multi-channel CS-SAR ADC which can simultaneously convert 4-channel signals with a sampling rate of one channelâs Nyquist rate. At 0.8 V and 1 MS/s, both chips achieve an effective Walden FoM of around 5 fJ/conversion-step.
This thesis also proposes a novel NS SAR ADC architecture that is simple, robust and low power for high-resolution applications. Compared to conventional âÎŁ ADCs, it replaces the power-hungry active integrator with a passive integrator which only requires one switch and two capacitors. Compared to previous 1st-order NS SAR ADC works, it achieves the best NS performance and can be easily extended to 2nd-order. A 1st-order 10-bit NS SAR ADC is fabricated in a 0.13 ”m process. Through NS, SNDR increases by 6 dB with OSR doubled, achieving a 12- bit ENOB at OSR = 8. An improved version of a 2nd-order 9-bit NS SAR ADC is designed and simulated in a 40 nm process. The SNDR increases by 10 dB with OSR doubled, achieving a 14-bit ENOB at OSR = 16. At a bandwidth of 312.5 kHz, the Schreier FoM is 181 dB and the Walden FoM is 12.5 fJ/conversion-step, proving that the proposed NS SAR ADC architecture can achieve high resolution and high power efficiency simultaneously.Electrical and Computer Engineerin
Image compression and energy harvesting for energy constrained sensors
Title from PDF of title page, viewed on June 21, 2013Dissertation advisor: Walter D. Leon-SalasVitaIncludes bibliographic references (pages 176-[187])Thesis (Ph.D.)--School of Computing and Engineering. University of Missouri--Kansas City, 2013The advances in complementary metal-oxide-semiconductor (CMOS) technology
have led to the integration of all components of electronic system into a single integrated
circuit. Ultra-low power circuit techniques have reduced the power consumption of circuits.
Moreover, solar cells with improved efficiency can be integrated on chip to harvest
energy from sunlight. As a result of all the above, a new class of miniaturized electronic
systems known as self-powered system on a chip has emerged. There is an increasing research
interest in the area of self-powered devices which provide cost-effective solutions
especially when these devices are used in the areas that changing or replacing batteries is
too costly. Therefore, image compression and energy harvesting are studied in this dissertation.
The integration of energy harvesting, image compression, and an image sensor
on the same chip provides the energy source to charge a battery, reduces the data rate, and improves the performance of wireless image sensors. Integrated circuits of image compression,
solar energy harvesting, and image sensors are studied, designed, and analyzed
in this work. In this dissertation, a hybrid image sensor that can perform the tasks of sensing and
energy harvesting is presented. Photodiodes of hybrid image sensor can be programmed
as image sensors or energy harvesting cells. The hybrid image sensor can harvest energy
in between frames, in sleep mode, and even when it is taking images. When sensing
images and harvesting energy are both needed at the same time, some pixels have to
work as sensing pixels, and the others have to work as solar cells. Since some pixels are
devoted to harvest energy, the resolution of the image will be reduced. To preserve the
resolution or to keep the fair resolution when a lot of energy collection is needed, image
reconstruction algorithms and compressive sensing theory provide solutions to achieve
a good image quality. On the other hand, when the battery has enough charge, image
compression comes into the picture. Multiresolution decomposition image compression
provides a way to compress image data in order to reduce the energy need from data
transmission. The solution provided in this dissertation not only harvests energy but also
saves energy resulting long lasting wireless sensors. The problem was first studied at the system level to identify the best system-level
configuration which was then implemented on silicon. As a proof of concept, a 32 x 32 array of hybrid image sensor, a 32 x 32 array of image sensor with multiresolution decomposition compression, and a compressive sensing converter have been designed
and fabricated in a standard 0.5 [micrometer] CMOS process. Printed circuit broads also have been
designed to test and verify the proposed and fabricated chips. VHDL and Matlab codes
were written to generate the proper signals to control, and read out data from chips. Image
processing and recovery were carried out in Matlab. DC-DC converters were designed to
boost the inherently low voltage output of the photodiodes. The DC-DC converter has
also been improved to increase the efficiency of power transformation.Introduction -- Hybrid imager system and circuit design -- Hybrid imager energy harvesting and image acquisition results and discussion -- Detailed description and mathematical analysis for a circuit of energy harvesting using on-chip solar cells -- Multiresolution decomposition for lossless and near-lossless compression -- An incremental [sigma-delta] converter for compressive sensing -- Detailed description of a sigma-delta random demodulator converter architecture for compressive sensing applications -- Conclusion -- Appendix A. Chip pin-out -- Appendix B. Schematics -- Appendix C. Pictures of custom PC
Integrated Circuits and Systems for Smart Sensory Applications
Connected intelligent sensing reshapes our society by empowering people with increasing new ways of mutual interactions. As integration technologies keep their scaling roadmap, the horizon of sensory applications is rapidly widening, thanks to myriad light-weight low-power or, in same cases even self-powered, smart devices with high-connectivity capabilities. CMOS integrated circuits technology is the best candidate to supply the required smartness and to pioneer these emerging sensory systems. As a result, new challenges are arising around the design of these integrated circuits and systems for sensory applications in terms of low-power edge computing, power management strategies, low-range wireless communications, integration with sensing devices. In this Special Issue recent advances in application-specific integrated circuits (ASIC) and systems for smart sensory applications in the following five emerging topics: (I) dedicated short-range communications transceivers; (II) digital smart sensors, (III) implantable neural interfaces, (IV) Power Management Strategies in wireless sensor nodes and (V) neuromorphic hardware
Ultra-low noise, high-frame rate readout design for a 3D-stacked CMOS image sensor
Due to the switch from CCD to CMOS technology, CMOS based image sensors have become
smaller, cheaper, faster, and have recently outclassed CCDs in terms of image quality. Apart
from the extensive set of applications requiring image sensors, the next technological
breakthrough in imaging would be to consolidate and completely shift the conventional CMOS
image sensor technology to the 3D-stacked technology. Stacking is recent and an innovative
technology in the imaging field, allowing multiple silicon tiers with different functions to be
stacked on top of each other. The technology allows for an extreme parallelism of the pixel
readout circuitry. Furthermore, the readout is placed underneath the pixel array on a 3D-stacked
image sensor, and the parallelism of the readout can remain constant at any spatial resolution of
the sensors, allowing extreme low noise and a high-frame rate (design) at virtually any sensor
array resolution.
The objective of this work is the design of ultra-low noise readout circuits meant for 3D-stacked
image sensors, structured with parallel readout circuitries. The readout circuitâs key
requirements are low noise, speed, low-area (for higher parallelism), and low power.
A CMOS imaging review is presented through a short historical background, followed by the
description of the motivation, the research goals, and the work contributions. The fundamentals
of CMOS image sensors are addressed, as a part of highlighting the typical image sensor features,
the essential building blocks, types of operation, as well as their physical characteristics and their
evaluation metrics. Following up on this, the document pays attention to the readout circuitâs
noise theory and the column converters theory, to identify possible pitfalls to obtain sub-electron
noise imagers. Lastly, the fabricated test CIS device performances are reported along with
conjectures and conclusions, ending this thesis with the 3D-stacked subject issues and the future
work. A part of the developed research work is located in the Appendices.Devido à mudança da tecnologia CCD para CMOS, os sensores de imagem em CMOS tornam se mais pequenos, mais baratos, mais råpidos, e mais recentemente, ultrapassaram os sensores
CCD no que respeita à qualidade de imagem. Para além do vasto conjunto de aplicaçÔes que
requerem sensores de imagem, o prĂłximo salto tecnolĂłgico no ramo dos sensores de imagem Ă©
o de mudar completamente da tecnologia de sensores de imagem CMOS convencional para a
tecnologia â3D-stackedâ. O empilhamento de chips Ă© relativamente recente e Ă© uma tecnologia
inovadora no campo dos sensores de imagem, permitindo vĂĄrios planos de silĂcio com diferentes
funçÔes poderem ser empilhados uns sobre os outros. Esta tecnologia permite portanto, um
paralelismo extremo na leitura dos sinais vindos da matriz de pĂxeis. AlĂ©m disso, num sensor de
imagem de planos de silĂcio empilhados, os circuitos de leitura estĂŁo posicionados debaixo da
matriz de pĂxeis, sendo que dessa forma, o paralelismo pode manter-se constante para qualquer
resolução espacial, permitindo assim atingir um extremo baixo ruĂdo e um alto debito de
imagens, virtualmente para qualquer resolução desejada.
O objetivo deste trabalho Ă© o de desenhar circuitos de leitura de coluna de muito baixo ruĂdo,
planeados para serem empregues em sensores de imagem â3D-stackedâ com estruturas
altamente paralelizadas. Os requisitos chave para os circuitos de leitura sĂŁo de baixo ruĂdo,
rapidez e pouca ĂĄrea utilizada, de forma a obter-se o melhor rĂĄcio.
Uma breve revisĂŁo histĂłrica dos sensores de imagem CMOS Ă© apresentada, seguida da
motivação, dos objetivos e das contribuiçÔes feitas. Os fundamentos dos sensores de imagem
CMOS sĂŁo tambĂ©m abordados para expor as suas caracterĂsticas, os blocos essenciais, os tipos
de operação, assim como as suas caracterĂsticas fĂsicas e suas mĂ©tricas de avaliação. No
seguimento disto, especial atenção Ă© dada Ă teoria subjacente ao ruĂdo inerente dos circuitos de
leitura e dos conversores de coluna, servindo para identificar os possĂveis aspetos que dificultem
atingir a tĂŁo desejada performance de muito baixo ruĂdo. Por fim, os resultados experimentais
do sensor desenvolvido sĂŁo apresentados junto com possĂveis conjeturas e respetivas conclusĂ”es,
terminando o documento com o assunto de empilhamento vertical de camadas de silĂcio, junto
com o possĂvel trabalho futuro
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