On the Design of Voltage-Controlled Sinusoidal Oscillators Using OTA's

A unified systematic approach to the design of voltage-controlled oscillators using only operational transconductance amplifiers (OTA's) and capacitors is discussed in this paper. Two classical oscillator models, i.e., quadrature and bandpass-based, are employed to generate several oscillator structures. They are very appropriate for silicon monolithic implementations. The resulting oscillation frequencies are proportional to the transconductance of the OTA and this makes the reported structures well-suited for building voltage controlled oscillators (VCO's). Amplitude stabilization circuits using both automatic gain control (AGC) mechanisms and limitation schemes are presented which are compatible with the transconductance amplifier capacitor oscillator (TACO). Experimental results from bipolar breadboard and CMOS IC prototypes are included showing good potential of OTA-based oscillators for high frequency VCO operation.Comisión Interministerial de Ciencia y Tecnología ME87-000

Theory Based on Device Current Clipping to Explain and Predict Performance Including Distortion of Power Amplifiers for Wireless Communication Systems

Power amplifiers are critical components in wireless communication systems that need to have high efficiency, in order to conserve battery life and minimise heat generation, and at the same time low distortion, in order to prevent increase of bit error rate due to constellation errors and adjacent channel interference. This thesis is aimed at meeting a need for greater understanding of distortion generated by power amplifiers of any technology, in order to help designers manage better the trade-off between obtaining high efficiency and low distortion. The theory proposed in this thesis to explain and predict the performance of power amplifiers, including distortion, is based on analysis of clipping of the power amplifier device current, and it is a major extension of previous clipping analyses, that introduces many key definitions and concepts. Distortion and other power amplifier metrics are determined in the form of 3-D surfaces that are plotted against PA class, which is determined by bias voltage, and input signal power level. It is shown that the surface of distortion exhibits very high levels due to clipping in the region where efficiency is high. This area of high distortion is intersected by a valley that is ‘L’-shaped. The 'L'-shaped valley is subject to a rotation that depends on the softness of the cut-off of the power amplifier device transfer characteristic. The distortion surface with rotated 'L'-shaped valley leads to predicted curves for distortion versus input signal power that match published measured curves for power amplifiers even using very simple device models. The distortion versus input signal power curves have types that are independent of technology. In class C, there is a single deep null. In the class AB range, that is divided into three sub-ranges, there may be two deep nulls (sub-range AB(B)), a ledge (sub-range AB(A)) or a shallow null with varying depth (sub-range AB(AB))

Nasics: A `Fabric-Centric\u27 Approach Towards Integrated Nanosystems

This dissertation addresses the fundamental problem of how to build computing systems for the nanoscale. With CMOS reaching fundamental limits, emerging nanomaterials such as semiconductor nanowires, carbon nanotubes, graphene etc. have been proposed as promising alternatives. However, nanoelectronics research has largely focused on a `device-first\u27 mindset without adequately addressing system-level capabilities, challenges for integration and scalable assembly. In this dissertation, we propose to develop an integrated nano-fabric, (broadly defined as nanostructures/devices in conjunction with paradigms for assembly, inter-connection and circuit styles), as opposed to approaches that focus on MOSFET replacement devices as the ultimate goal. In the `fabric-centric\u27 mindset, design choices at individual levels are made compatible with the fabric as a whole and minimize challenges for nanomanufacturing while achieving system-level benefits vs. scaled CMOS. We present semiconductor nanowire based nano-fabrics incorporating these fabric-centric principles called NASICs and N3ASICs and discuss how we have taken them from initial design to experimental prototype. Manufacturing challenges are mitigated through careful design choices at multiple levels of abstraction. Regular fabrics with limited customization mitigate overlay alignment requirements. Cross-nanowire FET devices and interconnect are assembled together as part of the uniform regular fabric without the need for arbitrary fine-grain interconnection at the nanoscale, routing or device sizing. Unconventional circuit styles are devised that are compatible with regular fabric layouts and eliminate the requirement for using complementary devices. Core fabric concepts are introduced and validated. Detailed analyses on device-circuit co-design and optimization, cascading, noise and parameter variation are presented. Benchmarking of nanowire processor designs vs. equivalent scaled 16nm CMOS shows up to 22X area, 30X power benefits at comparable performance, and with overlay precision that is achievable with present-day technology. Building on the extensive manufacturing-friendly fabric framework, we present recent experimental efforts and key milestones that have been attained towards realizing a proof-of-concept prototype at dimensions of 30nm and below

Concepts for 18/30 GHz satellite communication system, volume 1

Concepts for 18/30 GHz satellite communication systems are presented. Major terminal trunking as well as direct-to-user configurations were evaluated. Critical technologies in support of millimeter wave satellite communications were determined

Research and technology highlights of the Lewis Research Center

Highlights of research accomplishments of the Lewis Research Center for fiscal year 1984 are presented. The report is divided into four major sections covering aeronautics, space communications, space technology, and materials and structures. Six articles on energy are included in the space technology section

Carbon Nanotube Interconnect Modeling for Very Large Scale Integrated Circuits

In this research, we have studied and analyzed the physical and electrical properties of carbon nanotubes. Based on the reported models for current transport behavior in non-ballistic CNT-FETs, we have built a dynamic model for non-ballistic CNT-FETs. We have also extended the surface potential model of a non-ballistic CNT-FET to a ballistic CNT-FET and developed a current transport model for ballistic CNT-FETs. We have studied the current transport in metallic carbon nanotubes. By considering the electron-electron interactions, we have modified two-dimensional fluid model for electron transport to build a semi-classical one-dimensional fluid model to describe the electron transport in carbon nanotubes, which is regarded as one-dimensional system. Besides its accuracy compared with two-dimensional fluid model and Lüttinger liquid theory, one-dimensional fluid model is simple in mathematical modeling and easier to extend for electronic transport modeling of multi-walled carbon nanotubes and single-walled carbon nanotube bundles as interconnections. Based on our reported one-dimensional fluid model, we have calculated the parameters of the transmission line model for the interconnection wires made of single-walled carbon nanotube, multi-walled carbon nanotube and single-walled carbon nanotube bundle. The parameters calculated from these models show close agreements with experiments and other proposed models. We have also implemented these models to study carbon nanotube for on-chip wire inductors and it application in design of LC voltage-controlled oscillators. By using these CNT-FET models and CNT interconnects models, we have studied the behavior of CNT based integrated circuits, such as the inverter, ring oscillator, energy recovery logic; and faults in CNT based circuits

MODELING AND SPICE IMPLEMENTATION OF SILICON-ON-INSULATOR (SOI) FOUR GATE (G4FET) TRANSISTOR

As the device dimensions have reduced from micrometer to nanometer range, new bulk silicon devices are now facing many undesirable effects of scaling leading device engineers to look for new process technologies. Silicon-on-insulator (SOI) has emerged as a very promising candidate for resolving the major problems plaguing the bulk silicon technology. G4FET [G4FET] is a SOI transistor with four independent gates. Although G4FET has already shown great potential in different applications, the widespread adoption of a technology in circuit design is heavily dependent upon good SPICE (Simulation Program with Integrated Circuit Emphasis) models. CAD (Computer Aided Design) tools are now ubiquitous in circuit design and a fast, robust and accurate SPICE model is absolutely necessary to transform G4FET into a mainstream technology. The research goal is to develop suitable SPICE models for G4FET to aid circuit designers in designing innovative analog and digital circuits using this new transistor. The first phase of this work is numerical modeling of the G4FET where four different numerical techniques are implemented, each with its merits and demerits. The first two methods are based on multivariate Lagrange interpolation and multidimensional Bernstein polynomial. The third numerical technique is based on multivariate regression polynomial to aid modeling with dense gridded data. Another suitable alternative namely multidimensional linear and cubic spline interpolation is explored as the fourth numerical modeling approach to solve some of the problems resulting from single polynomial approximation. The next phase of modeling involves developing a macromodel combining already existing SPICE models of MOSFET (metal–oxide–semiconductor field-effect transistor) and JFET (junction-gate field-effect transistor). This model is easy to implement in circuit simulators and provides good results compared to already demonstrated experimental works with innovative G4FET circuits. The final phase of this work involves the development of a physics-based compact model of G4FET with some empirical fitting parameters. A model for depletion-all-around operation is implemented in circuit simulator based on previous work. Another simplified model, combining MOS and JFET action, is implemented in circuit simulator to model the accumulation mode operation of G4FET

Experimental characterization and control of stability margins in microwave amplifiers.

158 p.Robust design of microwave amplifiers implies the lack of undesired autonomous frequency components for operating conditions that can be very far from nominal. However, microwave amplifiers are prone to exhibit spurious oscillations of different nature and at different frequencies due to the large band gain of microwave transistors and their intrinsic non-linear behavior. To analyze the robustness of a design with respect to spurious oscillations, local stability analyses at simulation level could be performed. However, reliable models and fine circuit descriptions are not always availabe which often makes simulation impractical to analyze the robustness of an aplifier in terms of stability margin.In this context, the goal of this thesis is to develop an experimental technique to characterize critical resonances departing from accurate measurement data that are coherent with the amplifier normal functioning. The method is based on applying pole-zero identification technique to analyze the stability of microwave circuits in samll.signal and large-signal periodic regimes. A systematic methodology ofr microwave circuit stabilization has also been presented, since this can be very useful for the experimental contro of the stability margins.The proposed experimental technique for microwave circuit stability analysis has been applied to several prototypes in hybrid microstrip technology to demostrate its reliability: an L-band FET amplifier in DC regime, a dual mode WiFi-WIMAX amplifier in large-signal regime, and a GaN power amplifier in both regimes

Circuit Design and Compact Modeling in Printed Electronics Based on Inorganic Materials

Die gedruckte Elektronik ist ein im Vergleich zur konventionellen Siliziumtechnologie junges Forschungsgebiet. Die Idee hinter der gedruckten Elektronik ist es elektronische Bauteile wie Widerstände, Kapazitäten, Solarzellen, Dioden und Transistoren mit gängigen Druckmethoden herzustellen. Dabei ist es möglich die elektronischen Bauteile auf unbiegsamen Substrate, wie Glas oder Silizium, als auch auf biegsamen Substrate, wie Papier und Folie, zu drucken. Aufgrund des Druckprozesses, sind die Herstellungskosten gering, da drucken ein additiver Prozess ist und somit teure Masken obsolet sind. In einem Feldeffekttransistor, wird der Halbleiter zwischen zwei Elektroden (Drain- und Source) gedruckt. Die Drain- und Source-Elektroden werden dabei durch einen Vakuum- oder Druckprozess abgeschieden und strukturiert. Der halbleitende Kanal wird durch einen Dielektrikum von der Gate-Elektrode isoliert. Auch für das Dielektrikum und die Gate-Elektrode sind ein Vakuum- oder Druckprozess denkbar. Standardmäßig finden organische Materialien Einsatz in der gedruckten Elektronik. Leider weisen organische Halbleiter, in einem Feldeffekttransistor, nur eine geringe Ladungsträgerbeweglichkeit ($\leq 1$ cm$^2$(Vs)$^{-1}$) auf. Die niedrige Ladungsträgerbeweglichkeit führt zu einer geringen Ladungsträgerdichte im Halbleiter und als Resultat zu geringen Stromdichten. Auch sind größtenteils nur p-leitende Halbleiter für den Einsatz in Schaltungen vorhanden, weswegen die meisten Schaltungen nur p-leitende Feldeffekttransistoren besitzen. Ein weiterer Nachteil der organischen Elektronik ist, dass die eingesetzten Dielektrika mit dem Halbleiter eine mangelhafte Grenzfläche bildet. Deshalb sind Versorgungsspannungen in Bereich von 5 V keine Seltenheit. Eine interessante Alternative zu organischen Halbleitern sind Materialien die der Kategorie der Oxide zugeordnet sind. Zum Beispiel in Indiumoxid (In$_{2}$O$_{3}$) ist eine Ladungsträerbeweglichkeit um die 100 cm$^2$(Vs)$^{-1}$ messbar. Leider sind durch Oxide realisierte p-leitende Feldeffekttransistoren sehr selten, weshalb die meisten Schaltungen auf n-leitenden Feldeffekttransistoren basieren. Ein weiterer Nachteil von Metalloxidhalbleitern is das hohe Glühtemperaturen (\sim 400 \, ^\circC) benötigt werden um die richtige Kristallstruktur zu erzielen. Durch den Einsatz eines Elektrolyten, anstatt eines Dielektrikum, werden die benötigten hohen Versorgungsspannungen auf 1 V reduziert. Der Grund für die Reduzierung der Versorgungsspannung liegt in der hohen Kapazität ($\sim 5 \, \mu$F(cm)$^{-1}$), die sich zwischen der Gate-Elektrode und dem Kanal ausbildet. Die optimale Grenzfläche zwischen der Gate-Elektrode und dem Elektrolyten sowie als auch zwischen dem Elektrolyten und dem Kanal, wo sich eine Helmholtz-Doppelschicht ausbildet, ist der Grund für die hohe Kapazität. In dieser Arbeit, werden die Vorteile der hohen Ladungsträgerbeweglichkeit, resultierend von einem Indiumoxid-Kanal, und der niedrigen Versorgungsspannungen, durch den Einsatz eines Elektrolyten als Isolator, in einem gedruckten Transistor kombiniert. Daher ist das Ziel zunächst Transistoren basierend auf einem Elektrolyten und Indiumoxid-Kanal zu charakterisieren und zu modellieren. Auch werden Möglichkeiten zum Schaltungsentwurf mit der hier vorgestellten Transistortechnologie ausgearbeitet. Der Schaltungsentwurf wird anhand mikroelektronischen Zellen und Ringoszillator-Strukturen verifiziert. Wichtig für den Schaltungsentwurf sind Modelle die fähig sind die elektrischen Eigenschaften eines Transistors abzubilden. Dabei muss die simulierte Kurve Stetigkeit und Kontinuität aufweisen um Konvergenzprobleme während der Simulation zu verhindern. Zur Modellierung der elektrischen Eigenschaften und Ströme der Transistoren wird ein Modell basierend auf den Curtice-Modell entwickelt. Der Bereich über der Schwellwertspannung wird daher durch das Curtice-Modell abgebildet und der Bereich unter der Schwellspannung durch ein aus Siliziumtransistoren bekanntes Standard-Modell beschrieben. Kontinuität und Stetigkeit wird durch eine Interpolation zwischen den beiden Transistormodellen gewährleistet. Ein Verglich zwischen gemessenen und simulierten Daten zeigt das das Modell die hier vorgestellte Transistortechnologie sehr gut abbilden kann. Das entwickelte Transistormodel wird zur unterstützung des Schaltungsentwurf in einem Prozesskit (PDK) integriert. Dadurch ist das Verhalten einer Schaltung durch Simulation vorhersehbar. In der Simulation können auch der Einfluss der Umwelt, z.B. Luftfeuchtigkeit, auf die Transistoren analysiert werden. In der digitalen Schaltungstechnik wird ein p-leitender Feldeffekttransistor verwendet um ein Eingangssignal hochzusetzen, während um ein Signal runterzusetzen, ein n-leitender Feldeffekttransistor von Vorteil ist. Da p-leitende Oxide selten und unzuverlässig sind, wird der p-leitende Feldeffekttransistor durch einen Widerstand (Transistor-Widerstand-Logik (TRL)) oder einen n-leitenden Feldeffekttransistor (Transistor-Transistor-Logik (TTL)) ersetzt. Ein Inverter in TRL weist bei einer Versorgungsspannung von 1 V einen Verstärkungsfaktor von ungefähr -5 auf und eine Signalverzögerung von 0.9 ms. Die Oszillatorfrequenz im entsprechend Ringoszillator beträgt 296 Hz. Weitere Logikgatter (NAND, NOR und XOR) sind ebenfalls realisierbar mit TRL-Entwürfe. In TTL wird der p-leitende Feldeffekttransistor durch einen n-leitenden Verarmungstyps Feldeffekttransistor ersetzt. Die in der TTL entworfene Logikgatter verhalten sich identisch zu den TTR-Zellen aber die Frequenz vom Ringoszillator steigt bis in den unteren kHz-Bereich an. In TTL ist es ebenfalls möglich die Verlustleistung um einen Faktor von 6 zu reduzieren

Advances in Solid State Circuit Technologies

This book brings together contributions from experts in the fields to describe the current status of important topics in solid-state circuit technologies. It consists of 20 chapters which are grouped under the following categories: general information, circuits and devices, materials, and characterization techniques. These chapters have been written by renowned experts in the respective fields making this book valuable to the integrated circuits and materials science communities. It is intended for a diverse readership including electrical engineers and material scientists in the industry and academic institutions. Readers will be able to familiarize themselves with the latest technologies in the various fields