An Integrated Analog Readout for Multi-Frequency Bioimpedance Measurements

Bioimpedance spectroscopy is used in a wide range of biomedical applications. This paper presents an integrated analog readout, which employs synchronous detection to perform galvanostatic multi-channel, multi-frequency bioimpedance measurements. The circuit was fabricated in a 0.35-μm CMOS technology and occupies an area of 1.52 mm2. The effect of random dc offsets is investigated, along with the use of chopping to minimize them. Impedance measurements of a known RC load and skin (using commercially available electrodes) demonstrate the operation of the system over a frequency range up to 1 MHz. The circuit operates from a ±2.5 V power supply and has a power consumption of 3.4-mW per channel

A CMOS Magnitude/Phase Measurement Chip for Impedance Spectroscopy

The measurement of electrical impedance is used in a plethora of biomedical applications. The most common technique used is synchronous demodulation, which provides the real and imaginary parts of the impedance. However, in practice, the method requires elaborate calibration and matching between the injection and monitoring stages. This paper presents the integrated realization of an alternative method that is less intricate to implement. The circuit was fabricated in a 0.35-μm CMOS technology, occupies an active area of 0.4 mm2 , and dissipates about 21 mW of power from ±2.5 V supplies. The chip was used to measure equivalent RC circuits of the electrode-tissue interface over the frequency range of 100 Hz to 100 kHz, showing good correlation with the theoretical results

A New Proposal for OFCC-based Instrumentation Amplifier

This contribution puts forward a new voltage mode instrumentation amplifier (VMIA) based on operational floating current conveyor (OFCC). It presents high impedance at input terminals and provides output at low impedance making the proposal ideal for voltage mode operation. The proposed VMIA architecture has two stages - the first stage comprises of two OFCCs to sense input voltages and coverts the voltage difference to current while the second stage has single OFCC that converts the current to voltage. In addition it employs two resistors to provide gain and imposes no condition on the values of resistors.  The behavior of the proposed structure is also analyzed for OFCC non idealities namely finite transimpedance and tracking error. The proposal is verified through SPICE simulations using CMOS based schematic of OFCC. Experimental results, by bread boarding it using commercially available IC AD844, are also included

Mariner-Mars science subsystem

Mariner-Mars science subsystem - cosmic ray telescope, cosmic dust detector, trapped radiation detector, ionization chamber, plasma probe, magnetometer, and data processin

Contribution to time domain readout circuits design for multi-standard sensing system for low voltage supply and high-resolution applications

Mención Internacional en el título de doctorThis research activity has the purpose of open new possibilities in the design of capacitance-to-digital converters (CDCs) by developing a solution based on time domain conversion. This can be applied to applications related with the Internet-of-Things (IoT). These applications are present in any electronic devices where sensing is needed. To be able to reduce the area of the whole system with the required performance, micro-electromechanical systems (MEMS) sensors are used in these applications. We propose a new family of sensor readout electronics to be integrated with MEMS sensors. Within the time domain converters, Dual Slope (DS) topology is very interesting to explore a new compromise between performances, area and power consumption. DS topology has been extensively used in instrumentation. The simplicity and robustness of the blocks inside classical DS converters it is the main advantage. However, they are not efficient for applications where higher bandwidth is required. To extend the bandwidth, DS converters have been introduced into ΔΣ loops. This topology has been named as integrating converters. They increase the bandwidth compare to classical DS architecture but at the expense of higher complexity. In this work we propose the use of a new family of DS converters that keep the advantages of the classical architecture and introduce noise shaping. This way the bandwidth is increased without extra blocks. The Self-Compensated noise-shaped DS converter (the name given to the new topology) keeps the signal transfer function (STF) and the noise transfer function (NTF) of Integrating converters. However, we introduce a new arrangement in the core of the converter to do noise shaping without extra circuitry. This way the simplicity of the architecture is preserved. We propose to use the Self-Compensated DS converter as a CDC for MEMS sensors. This work makes a study of the best possible integration of the two blocks to keep the signal integrity considering the electromechanical behavior of the sensor. The purpose of this front-end is to be connected to any kind of capacitive MEMS sensor. However, to prove the concepts developed in this thesis the architecture has been connected to a pressure MEMS sensor. An experimental prototype was implemented in 130-nm CMOS process using the architecture mentioned before. A peak SNR of 103.9 dB (equivalent to 1Pa) has been achieved within a time measurement of 20 ms. The final prototype has a power consumption of 220 μW with an effective area of 0.317 mm2. The designed architecture shows good performance having competitive numbers against high resolution topologies in amplitude domain.Esta actividad de investigación tiene el propósito de explorar nuevas posibilidades en el diseño de convertidores de capacitancia a digital (CDC) mediante el desarrollo de una solución basada en la conversión en el dominio del tiempo. Estos convertidores se pueden utilizar en aplicaciones relacionadas con el mercado del Internet-de-las-cosas (IoT). Hoy en día, estas aplicaciones están presentes en cualquier dispositivo electrónico donde se necesite sensar una magnitud. Para poder reducir el área de todo el sistema con el rendimiento requerido, se utilizan sensores de sistemas micro-electromecánicos (MEMS) en estas aplicaciones. Proponemos una nueva familia de electrónica de acondicionamiento para integrar con sensores MEMS. Dentro de los convertidores de dominio de tiempo, la topología del doble-rampa (DS) es muy interesante para explorar un nuevo compromiso entre rendimiento, área y consumo de energía. La topología de DS se ha usado ampliamente en instrumentación. La simplicidad y la solidez de los bloques dentro de los convertidores DS clásicos es la principal ventaja. Sin embargo, no son eficientes para aplicaciones donde se requiere mayor ancho de banda. Para ampliar el ancho de banda, los convertidores DS se han introducido en bucles ΔΣ. Esta topología ha sido nombrada como Integrating converters. Esta topología aumenta el ancho de banda en comparación con la arquitectura clásica de DS, pero a expensas de una mayor complejidad. En este trabajo, proponemos el uso de una nueva familia de convertidores DS que mantienen las ventajas de la arquitectura clásica e introducen la configuración del ruido. De esta forma, el ancho de banda aumenta sin bloques adicionales. El convertidor Self-Compensated noise-shaped DS (el nombre dado a la nueva topología) mantiene la función de transferencia de señal (STF) y la función de transferencia de ruido (NTF) de los Integrating converters. Sin embargo, presentamos una nueva topología en el núcleo del convertidor para conformar el ruido sin circuitos adicionales. De esta manera, se preserva la simplicidad de la arquitectura. Proponemos utilizar el Self-Compensated noise-shaped DS como un CDC para sensores MEMS. Este trabajo hace un estudio de la mejor integración posible de los dos bloques para mantener la integridad de la señal considerando el comportamiento electromecánico del sensor. El propósito de este circuito de acondicionamiento es conectarse a cualquier tipo de sensor MEMS capacitivo. Sin embargo, para demostrar los conceptos desarrollados en esta tesis, la arquitectura se ha conectado a un sensor MEMS de presión. Se ha implementado dos prototipos experimentales en un proceso CMOS de 130-nm utilizando la arquitectura mencionada anteriormente. Se ha logrado una relación señal-ruido máxima de 103.9 dB (equivalente a 1 Pa) con un tiempo de medida de 20 ms. El prototipo final tiene un consumo de energía de 220 μW con un área efectiva de 0.317 mm2. La arquitectura diseñada muestra un buen rendimiento comparable con las arquitecturas en el dominio de la amplitud que muestran resoluciones equivalentes.Programa Oficial de Doctorado en Ingeniería Eléctrica, Electrónica y AutomáticaPresidente: Pieter Rombouts.- Secretario: Alberto Rodríguez Pérez.- Vocal: Dietmar Strãußnig

Design, analysis and implementation of a versatile low level radio frequency system for accelerating cavities

179 p.[ES]En esta tesis se describen diversas soluciones analógicas y digitales para realizar sistemas de control LLRF (Radio Frecuencia de Bajo Nivel) para cavidades resonantes de radiofrecuencia de aceleradores de partículas. Para analizar dichas cavidades, se desarrolla un modelo genérico que representa la respuesta dinámica de la cavidad bajo la influencia del haz de partículas. Después, se usa este modelo para desarrollar y analizar un sistema analógico de LLRF para el booster' del sincrotrón ALBA, así como un sistema LLRF digital para el linac de la futura Fuente Europea de Protones y Neutrones de Bilbao (ESS-Bilbao). A continuación, se presentan los detalles del diseño e implementación de los dos sistemas LLRF aludidos, así como los resultados experimentales obtenidos en distintas cavidades de radiofrecuencia, así verificando la validez de los dos diseños propuestos. También, se presenta el diseño básico de la electrónica de RF de un sistema de Monitorización de la Posición del Haz de Partículas (BPM) y los resultados preliminares obtenidos con un haz simulado en un banco de ensayos desarrollado al efecto. Hay dos consideraciones importantes a la hora de desarrollar un modelo eléctrico de cavidades radiofrecuencia útil para analizar el sistema o diseñar un lazo de LLRF: la respuesta transitoria y los desajustes de impedancia. Sin embargo, en la literatura raramente se consideran estas cuestiones de manera conjunta, y una suele prevalecer sobre la otra, dependiendo de si la cavidad de radiofrecuencia se mira desde una perspectiva de alta potencia o de LLRF. En esta tesis, en primer lugar, se desarrolla un modelo para representar los aspectos más importantes de la cavidad, incluyendo desajustes de impedancia, potencia reflejada y la respuesta transitoria, por ejemplo en el arranque del sistema o en los instantes de llegada del haz de partículas que carga la cavidad. Como un caso especial, se aplica el modelo a las cavidades RF del anillo de almacenamiento (storage ring) de ALBA, estudiando así los efectos de carga del haz (beam loading), el arranque del sistema y los retardos en la respuesta de los lazos de regulación. Para simular estos lazos, se emplea una técnica matemática para hacer corresponder la frecuencia resonante de la cavidad a banda base, obteniendo de esta manera un modelo equivalente en banda base de la cavidad, con una respuesta aproximadamente igual al modelo convencional RF, pero con una velocidad de simulación mucho mayor. A continuación, se presenta el diseño y la implementación del sistema de LLRF analógico del booster' de ALBA, basado en lazos de realimentación de las señales IQ del sistema. Se miden los parámetros importantes del LLRF operando la cavidad tanto a baja como a alta potencia de RF, verificando así el diseño propuesto. Finalmente, se presenta el diseño, implementación y diversos resultados experimentales del sistema LLRF digital pulsado que hemos desarrollado para el Cuadrupolo de Radio Frecuencia (RFQ) del Rutherford Appleton Laboratory - Front End Test Stand (Oxfordshire, Inglaterra) y para el futuro linac de ESS-Bilbao. En lugar de emplear un front-end' analógico estándar que convierta las señales medidas en la cavidad a una Frecuencia Intermedia (IF) para a continuación submuestrear este señal, en este diseño usamos un demodulador IQ analógico, que transforma directamente las señales RF medidas en sus componentes En-fase (I) y Cuadratura (Q) en banda base. La ventaja principal de usar este método es eliminar la necesidad para un sistema preciso y complejo de sincronización y timing', lo cual da lugar a un sistema LLRF simple y versátil que puede servir para un rango grande de frecuencias y virtualmente para cualquier aplicación LLRF, sean pulsadas, en rampa o de onda continua (CW). Los errores asociados al uso de demoduladores de IQ analógicos han sido identificados y corregidos mediante algoritmos implementados en la FPGA y por medio del ajuste apropiado de los parámetros del lazo de control. Además, se ha desarrollado un modelo equivalente en banda base del RFQ en MATLAB-Simulink para estudiar su respuesta transitoria en condiciones de carga del haz y en presencia de errores de fase y retardos. Los resultados experimentales obtenidos con una cavidad de prueba y un modelo en cobre del RFQ verifican que en lazo cerrado pueden obtenerse campos acelerantes con niveles de estabilidad de amplitud y fase superiores al 1 por ciento y un grado respectivamente, además de un margen de fase mayor de +/- 50 grados que confiere robustez al sistema, conservando al mismo tiempo la linealidad y el ancho de banda de los lazos de regulación, y cumpliendo por tanto sobradamente las especificaciones requeridas para el acelerador[EN]This thesis describes analog and digital Low-Level Radio Frequency (LLRF) solutions applied to RF cavities of particle accelerators. For cavity analysis, a generic electrical model is developed to represent the cavity dynamic response under a beam. This model is then used as the basis for the design and analysis of two LLRF systems being the analog LLRF of the ALBA booster and the digital LLRF of the future Bilbao Proton and Neutron Source (ESS-Bilbao) linac. Details of the design and implementation of both LLRF systems are given followed by the experimental results obtained with di erent types of cavities verifying the validity of both LLRF systems. Also, the basic design of the ESS-Bilbao Beam Position Monitoring (BPM) RF electronics is described and the preliminary results obtained with a BPM test bench are presented. There are two important considerations in the development of an electrical model analogy for RF cavities to be used for system analysis or LLRF loop design, being: transient response and cavity impedance mismatches. In the literature, however, either one or both of these issues are often neglected depending on whether the RF cavity is being looked at from a high-power or a LLRF perspective. In this thesis, in the rst place, a transient model for RF cavities under beam loading is developed so that it represents the important RF aspects of the cavity such as impedance mismatches and re ected voltage as well as its transient response, for example at start-up or upon beam arrival. As a special case, the model is applied to the RF cavity of the ALBA storage ring to study the e ects arising from beam loading, system start-up and delays on the performance of the LLRF regulation loops. For the simulation of the regulation loops in time domain a mathematical technique is introduced to map the cavity resonant frequency to baseband, leading to a baseband-equivalent model for the cavity with almost the same results as the conventional RF model but with signi cantly higher simulation speed. In the continuation, the design and implementation of the IQ-based analog LLRF system for the ALBA booster is presented. The important LLRF parameters have been measured with the cavity running under low and high RF power and compared to the speci cations verifying that all the requirements can be met with the proposed LLRF design. Finally, the design and some performance results of the pulsed digital LLRF for the RFQ (Radio Frequency Quadrupole) systems of Rutherford Appleton Laboratory - Front End Test Stand and the future ESS-Bilbao linac are presented. Contrary to the standard digital LLRF front-end in which the cavity probe voltage is rst down converted to an Intermediate Frequency (IF) and then subsampled, in this design, an analog IQ demodulator has been used to directly convert the probe voltage to I (In-phase) and Q (Quadrature-phase) components in baseband. The main advantage of this method is that the need for a precise synchronization and timing system for down-conversion and ADC sampling is eliminated leading to a simple and versatile design which can be used for a large variety of RF frequencies and virtually any LLRF application including CW, ramping and pulsed. The errors associated with the use of analog IQ demodulators have been identi ed and corrected by FPGA algorithms and proper setting of the control loop parameters. Furthermore, a basebandequivalent model for the RF plant is developed in MATLAB-Simulink to study the RFQ transient response under beam loading in the presence of phase and delay errors. The practical results obtained with a mock-up cavity and an RFQ cold model verify that amplitude and phase stabilities in the acceleration elds down to a fraction of one percent and one degree, and phase margins larger than 50 can be achieved with this method preserving the linearity and bandwidth of the regulation loops and ful lling the required speci cations for the accelerator

Low-power Wearable Healthcare Sensors

Advances in technology have produced a range of on-body sensors and smartwatches that can be used to monitor a wearer’s health with the objective to keep the user healthy. However, the real potential of such devices not only lies in monitoring but also in interactive communication with expert-system-based cloud services to offer personalized and real-time healthcare advice that will enable the user to manage their health and, over time, to reduce expensive hospital admissions. To meet this goal, the research challenges for the next generation of wearable healthcare devices include the need to offer a wide range of sensing, computing, communication, and human–computer interaction methods, all within a tiny device with limited resources and electrical power. This Special Issue presents a collection of six papers on a wide range of research developments that highlight the specific challenges in creating the next generation of low-power wearable healthcare sensors

Design/cost tradeoff studies. Earth Observatory Satellite system definition study (EOS)

The results of design/cost tradeoff studies conducted during the Earth Observatory Satellite system definition studies are presented. The studies are concerned with the definition of a basic modular spacecraft capable of supporting a variety of operational and/or research and development missions, with the deployment either by conventional launch vehicles or by means of the space shuttle. The three levels investigated during the study are: (1) subsystem tradeoffs, (2) spacecraft tradeoffs, and (3) system tradeoffs. The range of requirements which the modular concept must span is discussed. The mechanical, thermal, power, data and electromagnetic compatibility aspects of modularity are analyzed. Other data are provided for the observatory design concept, the payloads, integration and test, the ground support equipment, and ground data management systems

AROD test model hardware, volume 2 Final report

Engineering design data on vehicle-borne subsystems of airborne range and orbit determination syste