Temperature Characterization of a Fully-synthesizable Rail-to-Rail Dynamic Voltage Comparator operating down to 0.15-V

This paper deals with the performance/temperature tradeoff in an ultra-low voltage, ultra-low power rail-to-rail dynamic voltage comparator made solely by digital standard cells. The digital nature of the comparator makes its design technology portable also enabling its operation at very low supply voltages down to deep sub-threshold. In particular, as sub-threshold circuits have a significant temperature dependence, this paper focuses on the comparator performance under different supply voltages and temperatures.Measurements performed on a 180nm testchip show correct operation under rail-to-rail common-mode input at a supply voltage ranging from 0.6V down to 0.15V. Moreover, the measurements under temperature variations of offset, clock-to-output delay, and power in the range from -25 °C to 75 °C show the respective performance trade-offs

A Construction Kit for Efficient Low Power Neural Network Accelerator Designs

Implementing embedded neural network processing at the edge requires efficient hardware acceleration that couples high computational performance with low power consumption. Driven by the rapid evolution of network architectures and their algorithmic features, accelerator designs are constantly updated and improved. To evaluate and compare hardware design choices, designers can refer to a myriad of accelerator implementations in the literature. Surveys provide an overview of these works but are often limited to system-level and benchmark-specific performance metrics, making it difficult to quantitatively compare the individual effect of each utilized optimization technique. This complicates the evaluation of optimizations for new accelerator designs, slowing-down the research progress. This work provides a survey of neural network accelerator optimization approaches that have been used in recent works and reports their individual effects on edge processing performance. It presents the list of optimizations and their quantitative effects as a construction kit, allowing to assess the design choices for each building block separately. Reported optimizations range from up to 10'000x memory savings to 33x energy reductions, providing chip designers an overview of design choices for implementing efficient low power neural network accelerators

Digital-based analog processing in nanoscale CMOS ICs for IoT applications

The Internet-of-Things (IoT) concept has been opening up a variety of applications, such as urban and environmental monitoring, smart health, surveillance, and home automation. Most of these IoT applications require more and more power/area efficient Complemen tary Metal–Oxide–Semiconductor (CMOS) systems and faster prototypes (lower time-to market), demanding special modifications in the current IoT design system bottleneck: the analog/RF interfaces. Specially after the 2000s, it is evident that there have been significant improvements in CMOS digital circuits when compared to analog building blocks. Digital circuits have been taking advantage of CMOS technology scaling in terms of speed, power consump tion, and cost, while the techniques running behind the analog signal processing are still lagging. To decrease this historical gap, there has been an increasing trend in finding alternative IC design strategies to implement typical analog functions exploiting Digital in-Concept Design Methodologies (DCDM). This idea of re-thinking analog functions in digital terms has shown that Analog ICs blocks can also avail of the feature-size shrinking and energy efficiency of new technologies. This thesis deals with the development of DCDM, demonstrating its compatibility for Ultra-Low-Voltage (ULV) and Power (ULP) IoT applications. This work proves this state ment through the proposing of new digital-based analog blocks, such as an Operational Transconductance Amplifiers (OTAs) and an ac-coupled Bio-signal Amplifier (BioAmp). As an initial contribution, for the first time, a silicon demonstration of an embryonic Digital-Based OTA (DB-OTA) published in 2013 is exhibited. The fabricated DB-OTA test chip occupies a compact area of 1,426 µm2 , operating at supply voltages (VDD) down to 300 mV, consuming only 590 pW while driving a capacitive load of 80pF. With a Total Harmonic Distortion (THD) lower than 5% for a 100mV input signal swing, its measured small-signal figure of merit (FOMS) and large-signal figure of merit (FOML) are 2,101 V −1 and 1,070, respectively. To the best of this thesis author’s knowledge, this measured power is the lowest reported to date in OTA literature, and its figures of merit are the best in sub-500mV OTAs reported to date. As the second step, mainly due to the robustness limitation of previous DB-OTA, a novel calibration-free digital-based topology is proposed, named here as Digital OTA (DIG OTA). A 180-nm DIGOTA test chip is also developed exhibiting an area below the 1000 µm2 wall, 2.4nW power under 150pF load, and a minimum VDD of 0.25 V. The proposed DIGOTA is more digital-like compared with DB-OTA since no pseudo-resistor is needed. As the last contribution, the previously proposed DIGOTA is then used as a building block to demonstrate the operation principle of power-efficient ULV and ultra-low area (ULA) fully-differential, digital-based Operational Transconductance Amplifier (OTA), suitable for microscale biosensing applications (BioDIGOTA) such as extreme low area Body Dust. Measured results in 180nm CMOS confirm that the proposed BioDIGOTA can work with a supply voltage down to 400 mV, consuming only 95 nW. The BioDIGOTA layout occupies only 0.022 mm2 of total silicon area, lowering the area by 3.22X times compared to the current state of the art while keeping reasonable system performance, such as 7.6 Noise Efficiency Factor (NEF) with 1.25 µVRMS input-referred noise over a 10 Hz bandwidth, 1.8% of THD, 62 dB of the common-mode rejection ratio (CMRR) and 55 dB of power supply rejection ratio (PSRR). After reviewing the current DCDM trend and all proposed silicon demonstrations, the thesis concludes that, despite the current analog design strategies involved during the analog block development

Digital-Based Analog Processing in Nanoscale CMOS ICs for IoT Applications

L'abstract è presente nell'allegato / the abstract is in the attachmen

ISM-Band Energy Harvesting Wireless Sensor Node

In recent years, the interest in remote wireless sensor networks has grown significantly, particularly with the rapid advancements in Internet of Things (IoT) technology. These networks find diverse applications, from inventory tracking to environmental monitoring. In remote areas where grid access is unavailable, wireless sensors are commonly powered by batteries, which imposes a constraint on their lifespan. However, with the emergence of wireless energy harvesting technologies, there is a transformative potential in addressing the power challenges faced by these sensors. By harnessing energy from the surrounding environment, such as solar, thermal, vibrational, or RF sources, these sensors can potentially operate autonomously for extended periods. This innovation not only enhances the sustainability of wireless sensor networks but also paves the way for a more energy-efficient and environmentally conscious approach to data collection and monitoring in various applications. This work explores the development of an RF-powered wireless sensor node in 22nm FDSOI technology working in the ISM band for energy harvesting and wireless data transmission. The sensor node encompasses power-efficient circuits, including an RF energy harvesting module equipped with a multi-stage RF Dickson rectifier, a robust power management unit, a DLL and XOR-based frequency synthesizer for RF carrier generation, and a class E power amplifier. To ensure the reliability of the WSN, a dedicated wireless RF source powers up the WSN. Additionally, the RF signal from this dedicated source serves as the reference frequency input signal for synthesizing the RF carrier for wireless data transmission, eliminating the need for an on-chip local oscillator. This approach achieves high integration and proves to be a cost-effective implementation of efficient wireless sensor nodes. The receiver and energy harvester operate at 915 MHz Frequency, while the transmitter functions at 2.45 GHz, employing On-Off Keying (OOK) for data modulation. The WSN utilizes an efficient RF rectifier design featuring a remarkable power conversion efficiency, reaching 55% at an input power of -14 dBm. Thus, the sensor node can operate effectively even with an extremely low RF input power of -25 dBm. The work demonstrates the integration of the wireless sensor node with an ultra-low-power temperature sensor, designed using 65 nm CMOS technology. This temperature sensor features an ultra-low power consumption of 60 nW and a Figure of Merit (FOM) of 0.022 [nJ.K-2]. The WSN demonstrated 55% power efficiency at a TX output power of -3.8 dBm utilizing a class E power amplifier

A fully integrated autonomous power management system with high power capacity and novel MPPT for thermoelectric energy harvesters in IoT/wearable applications

This paper reports a fully integrated autonomous power management system for thermoelectric energy harvesting with application in batteryless IoT/Wearable devices. The novel maximum power point tracking (MPPT) algorithm does not require open circuit voltage measurement. The proposed system delivers 0.5 mA current with 1 V regulated output based on simulations, which is the highest output current for a fully integrated converter reported in the literature for ultra-low voltage applications, to the best knowledge of the authors. Regulated 1 V output can be achieved for load range >2 k Omega, and input voltage range >140 mV. The circuit has been implemented in UMC-180nm standard CMOS technology and simulated

An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics

Near-sensor data analytics is a promising direction for IoT endpoints, as it minimizes energy spent on communication and reduces network load - but it also poses security concerns, as valuable data is stored or sent over the network at various stages of the analytics pipeline. Using encryption to protect sensitive data at the boundary of the on-chip analytics engine is a way to address data security issues. To cope with the combined workload of analytics and encryption in a tight power envelope, we propose Fulmine, a System-on-Chip based on a tightly-coupled multi-core cluster augmented with specialized blocks for compute-intensive data processing and encryption functions, supporting software programmability for regular computing tasks. The Fulmine SoC, fabricated in 65nm technology, consumes less than 20mW on average at 0.8V achieving an efficiency of up to 70pJ/B in encryption, 50pJ/px in convolution, or up to 25MIPS/mW in software. As a strong argument for real-life flexible application of our platform, we show experimental results for three secure analytics use cases: secure autonomous aerial surveillance with a state-of-the-art deep CNN consuming 3.16pJ per equivalent RISC op; local CNN-based face detection with secured remote recognition in 5.74pJ/op; and seizure detection with encrypted data collection from EEG within 12.7pJ/op.Comment: 15 pages, 12 figures, accepted for publication to the IEEE Transactions on Circuits and Systems - I: Regular Paper

Ultralow power voltage reference circuit for implantable devices in standard CMOS technology

This is the peer reviewed version of the following article: Óscar Pereira-Rial, Paula López, Juan M. Carrillo, Victor M. Brea and Diego Cabello (2019) Ultralow power voltage reference circuit for implantable devices in standard CMOS technology. International journal of circuit theory and applications, 47 (7), 991-1005, which has been published in final form at https://doi.org/10.1002/cta.2643. This article may be used for non-commercial purposes in accordance with Wiley Terms and Conditions for Use of Self-Archived VersionsAn ultralow power CMOS voltage reference for body implantable devices is presented in this paper. The circuit core consists of only regular threshold voltage PMOS transistors, thus leading to a very reduced output voltage dispersion, defined as σ/μ, and extremely low power consumption. A mathematical model of the generated reference voltage was obtained by solving circuit equations, and its numerical solution has been validated by extensive electrical simulations using a commercial circuit simulator. The proposed solution incorporates a passive RC low‐pass filter, to enhance power supply rejection (PSR) over a wide frequency range, and a speed‐up section, to accelerate the switching‐on of the circuit. The prototype was implemented in 0.18 μm standard CMOS technology and is able to operate with supply voltages ranging from 0.7 to 1.8 V providing a measured output voltage value of 584.2 mV at the target temperature of 36° C. The measured σ/μ dispersion of the reference voltage generated is 0.65% without the need of trimming. At the minimum supply of 0.7 V, the experimental power consumption is 64.5 pW, while the measured PSR is kept below –60 dB from DC up to the MHz frequency rangeThis work has been partially funded by the Spanish government projects TEC2015‐66878‐C3‐3‐R (MINECO/FEDER) and RTI2018‐097088‐B‐C32 (FEDER), by the Xunta de Galicia under project ED431C2017/69, by the Consellería de Cultura, Educación e Ordenación Universitaria (accreditation 2016‐2019, ED431G/08 and reference competitive group 2017‐2020, ED431C 2017/69), by the Junta de Extremadura R&D Plan, and the European Fund for Regional Development (EFRD) under Grant IB18079S

Integrated Circuits for Programming Flash Memories in Portable Applications

Smart devices such as smart grids, smart home devices, etc. are infrastructure systems that connect the world around us more than before. These devices can communicate with each other and help us manage our environment. This concept is called the Internet of Things (IoT). Not many smart nodes exist that are both low-power and programmable. Floating-gate (FG) transistors could be used to create adaptive sensor nodes by providing programmable bias currents. FG transistors are mostly used in digital applications like Flash memories. However, FG transistors can be used in analog applications, too. Unfortunately, due to the expensive infrastructure required for programming these transistors, they have not been economical to be used in portable applications. In this work, we present low-power approaches to programming FG transistors which make them a good candidate to be employed in future wireless sensor nodes and portable systems. First, we focus on the design of low-power circuits which can be used in programming the FG transistors such as high-voltage charge pumps, low-drop-out regulators, and voltage reference cells. Then, to achieve the goal of reducing the power consumption in programmable sensor nodes and reducing the programming infrastructure, we present a method to program FG transistors using negative voltages. We also present charge-pump structures to generate the necessary negative voltages for programming in this new configuration