Multiplierless CSD techniques for high performance FPGA implementation of digital filters.

I leverage FastCSD to develop a new, high performance iterative multiplierless structure based on a novel real-time CSD recoding, so that more zero partial products are introduced. Up to 66.7% zero partial products occur compared to 50% in the traditional modified Booth's recoding. Also, this structure reduces the non-zero partial products to a minimum. As a result, the number of arithmetic operations in the carry-save structure is reduced. Thus, an overall speed-up, as well as low-power consumption can be achieved. Furthermore, because the proposed structure involves real time CSD recoding and does not require a fixed value for the multiplier input to be known a priori, the proposed multiplier can be applied to implement digital filters with non-fixed filter coefficients, such as adaptive filters.My work is based on a dramatic new technique for converting between 2's complement and CSD number systems, and results in high-performance structures that are particularly effective for implementing adaptive systems in reconfigurable logic.My research focus is on two key ideas for improving DSP performance: (1) Develop new high performance, efficient shift-add techniques ("multiplierless") to implement the multiply-add operations without the need for a traditional multiplier structure. (2) There is a growing trend toward design prototyping and even production in FPGAs as opposed to dedicated DSP processors or ASICs; leverage this trend synergistically with the new multiplierless structures to improve performance.Implementation of digital signal processing (DSP) algorithms in hardware, such as field programmable gate arrays (FPGAs), requires a large number of multipliers. Fast, low area multiply-adds have become critical in modern commercial and military DSP applications. In many contemporary real-time DSP and multimedia applications, system performance is severely impacted by the limitations of currently available speed, energy efficiency, and area requirement of an onboard silicon multiplier.I also introduce a new multi-input Canonical Signed Digit (CSD) multiplier unit, which requires fewer shift/add/subtract operations and reduced CSD number conversion overhead compared to existing techniques. This results in reduced power consumption and area requirements in the hardware implementation of DSP algorithms. Furthermore, because all the products are produced simultaneously, the multiplication speed and thus the throughput are improved. The multi-input multiplier unit is applied to implement digital filters with non-fixed filter coefficients, such as adaptive filters. The implementation cost of these digital filters can be further reduced by limiting the wordlength of the input signal with little or no sacrifice to the filter performance, which is confirmed by my simulation results. The proposed multiplier unit can also be applied to other DSP algorithms, such as digital filter banks or matrix and vector multiplications.Finally, the tradeoff between filter order and coefficient length in the design and implementation of high-performance filters in Field Programmable Gate Arrays (FPGAs) is discussed. Non-minimum order FIR filters are designed for implementation using Canonical Signed Digit (CSD) multiplierless implementation techniques. By increasing the filter order, the length of the coefficients can be decreased without reducing the filter performance. Thus, an overall hardware savings can be achieved.Adaptive system implementations require real-time conversion of coefficients to Canonical Signed Digit (CSD) or similar representations to benefit from multiplierless techniques for implementing filters. Multiplierless approaches are used to reduce the hardware and increase the throughput. This dissertation introduces the first non-iterative hardware algorithm to convert 2's complement numbers to their CSD representations (FastCSD) using a fixed number of shift and logic operations. As a result, the power consumption and area requirements required for hardware implementation of DSP algorithms in which the coefficients are not known a priori can be greatly reduced. Because all CSD digits are produced simultaneously, the conversion speed and thus the throughput are improved when compared to overlap-and-scan techniques such as Booth's recoding

High throughput spatial convolution filters on FPGAs

Digital signal processing (DSP) on field- programmable gate arrays (FPGAs) has long been appealing because of the inherent parallelism in these computations that can be easily exploited to accelerate such algorithms. FPGAs have evolved significantly to further enhance the mapping of these algorithms, included additional hard blocks, such as the DSP blocks found in modern FPGAs. Although these DSP blocks can offer more efficient mapping of DSP computations, they are primarily designed for 1-D filter structures. We present a study on spatial convolutional filter implementations on FPGAs, optimizing around the structure of the DSP blocks to offer high throughput while maintaining the coefficient flexibility that other published architectures usually sacrifice. We show that it is possible to implement large filters for large 4K resolution image frames at frame rates of 30–60 FPS, while maintaining functional flexibility

Diseño hardware de la transformada wavelet discreta: un análisis de complejidad, precisión y frecuencia de operación

The purpose of this paper is to present a comparative analysis of hardware design of the Discrete Wavelet Transform (DWT) in terms of three design goals: accuracy, hardware cost and operating frequency. Every design should take into account the following facts: method (non-polyphase, polyphase and lifting), topology (multiplier-based and multiplierless-based), structure (conventional or pipelined), and quantization format (floatingpoint, fixed-point, CSD or integer). Since DWT is widely used in several applications (e.g. compression, filtering, coding, pattern recognition among others), selection of adequate parameters plays an important role in the performance of these systems.El propósito de este documento es presentar un análisis comparativo de esquemas hardware de la Transformada Wavelet Discreta, DWT, en términos de tres objetivos de diseño: precisión, complejidad y frecuencia de operación. Cada diseño debe considerar los siguientes aspectos: método (no polifásico, polifásico y lifting), topología (basados en multiplicadores y sin multiplicadores), estructura (convencional o pipeline) y formato de cuantización (punto flotante, punto fijo, CSD o entero). Dado que la DWT es ampliamente utilizada en diversas aplicaciones (por ejemplo en compresión, filtrado, codificación, reconocimiento de patrones, entre otras), la selección adecuada de parámetros de diseño desempeña un papel importante en el diseño de estos sistemas

Reconfigurable Adaptive Multiple Transform Hardware Solutions for Versatile Video Coding

Computer aided design is nowadays a must to quickly provide optimized circuits, to cope with stringent time to market constraints, and to be able to guarantee colliding constrained requirements. Design automation is exploited, whenever possible, to speed up the design process and relieve the developers from error prone customization, optimization and tuning phases. In this work we study the possibility of adopting automated algorithms for the optimization of reconfigurable multiple constant multiplication circuits. In particular, an exploration of novel reconfigurable Adaptive Multiple Transform circuital solutions adoptable in video coding applications has been conducted. These solutions have also been compared with the unique similar work at the state of the art, revealing to be beneficial under certain constraints. Moreover, the proposed approach has been generalized with some guidelines helpful to designers facing similar problems

Joint Optimization of Low-power DCT Architecture and Effcient Quantization Technique for Embedded Image Compression

International audienceThe Discrete Cosine Transform (DCT)-based image com- pression is widely used in today's communication systems. Signi cant research devoted to this domain has demonstrated that the optical com- pression methods can o er a higher speed but su er from bad image quality and a growing complexity. To meet the challenges of higher im- age quality and high speed processing, in this chapter, we present a joint system for DCT-based image compression by combining a VLSI archi- tecture of the DCT algorithm and an e cient quantization technique. Our approach is, rstly, based on a new granularity method in order to take advantage of the adjacent pixel correlation of the input blocks and to improve the visual quality of the reconstructed image. Second, a new architecture based on the Canonical Signed Digit and a novel Common Subexpression Elimination technique is proposed to replace the constant multipliers. Finally, a recon gurable quantization method is presented to e ectively save the computational complexity. Experimental results obtained with a prototype based on FPGA implementation and com- parisons with existing works corroborate the validity of the proposed optimizations in terms of power reduction, speed increase, silicon area saving and PSNR improvement

An Architecture for On board Frequency Domain Analysis of Launch Vehicle Vibration Signals

The dynamic properties of the airborne structures plays a crucial role in the stability of the vehicle during flight. Modal and spectral behaviour of the structures are simulated and analysed. Ground tests are carried out with environmental conditions close to the flight conditions, with some assumptions. Subsequently, based on the flight telemetered data, the on-board mission algorithm and the auto-pilot filter coefficients are fine tuned. An attempt is made in this paper to design a novel architecture for analysing the modal and spectral random vibration signals on-board the flight vehicle and to identify the dominant frequencies. Based on the analysed results, the mission mode algorithm and the filter coefficients can be fine tuned on-board for better effectiveness in control and providing more stability. Three types of windows viz. Hann, Hamming and Blackman-Harris are configured with a generalised equation using FIR filter structure. The overlapping of the input signal data for better inclusiveness of the real-time data is implemented with BRAM. The domain conversion of the data from time domain to frequency domain is carried out with FFT using Radix-2 BF architecture. The FFT output data are processed for calculating the power spectral density. The dominant frequency is identified using the array search method and Goldschmidt algorithm is utilised for the averaging of the PSDs for better precision. The proposed architecture is synthesised, implemented and tested with both Synthetic and doppler signal of 300 Hz spot frequency padded with Gaussian white noise. The results are highly satisfactory in identifying the spot frequency and generating the PSD array