MOSFET zero-temperature-coefficient (ZTC) effect modeling anda analysis for low thermal sensitivity analog applications

Continuing scaling of Complementary Metal-Oxide-Semiconductor (CMOS) technologies brings more integration and consequently temperature variation has become more aggressive into a single die. Besides, depending on the application, room ambient temperature may also vary. Therefore, procedures to decrease thermal dependencies of eletronic circuit performances become an important issue to include in both digital and analog Integrated Circuits (IC) design flow. The main purpose of this thesis is to present a design methodology for a typical CMOS Analog design flow to make circuits as insensitivity as possible to temperature variation. MOSFET Zero Temperature Coefficient (ZTC) and Transconductance Zero Temperature Coefficient (GZTC) bias points are modeled to support it. These are used as reference to deliver a set of equations that explains to analog designers how temperature will change transistor operation and hence the analog circuit behavior. The special bias conditions are analyzed using a MOSFET model that is continuous from weak to strong inversion, and both are proven to occur always from moderate to strong inversion operation in any CMOS fabrication process. Some circuits are designed using proposed methodology: two new ZTC-based current references, two new ZTC-based voltage references and four classical Gm-C circuits biased at GZTC bias point (or defined here as GZTC-C filters). The first current reference is a Self-biased CMOS Current Reference (ZSBCR), which generates a current reference of 5 A. It is designed in an 180 nm process, operating with a supply voltage from 1.4V to 1.8 V and occupying around 0:010mm2 of silicon area. From circuit simulations the reference shows an effective temperature coefficient (TCeff ) of 15 ppm/oC from 45 to +85oC, and a fabrication process sensitivity of = = 4:5%, including average process and local mismatch. Simulated power supply sensitivity is estimated around 1%/V. The second proposed current reference is a Resistorless Self-Biased ZTC Switched Capacitor Current Reference (ZSCCR). It is also designed in an 180 nm process, resulting a reference current of 5.88 A under a supply voltage of 1.8 V, and occupying a silicon area around 0:010mm2. Results from circuit simulation show an TCeff of 60 ppm/oC from -45 to +85 oC and a power consumption of 63 W. The first proposed voltage reference is an EMI Resisting MOSFET-Only Voltage Reference (EMIVR), which generates a voltage reference of 395 mV. The circuit is designed in a 130 nm process, occupying around 0.0075 mm2 of silicon area while consuming just 10.3 W. Post-layout simulations present a TCeff of 146 ppm/oC, for a temperature range from 55 to +125oC. An EMI source of 4 dBm (1 Vpp amplitude) injected into the power supply of circuit, according to Direct Power Injection (DPI) specification results in a maximum DC Shift and Peak-to-Peak ripple of -1.7 % and 35.8m Vpp, respectively. The second proposed voltage reference is a 0.5V Schottky-based Voltage Reference (SBVR). It provides three voltage reference outputs, each one utilizing different threshold voltage MOSFETs (standard-VT , low-VT , and zero-VT ), all available in adopted 130 nm CMOS process. This design results in three different and very low reference voltages: 312, 237, and 51 mV, presenting a TCeff of 214, 372, and 953 ppm/oC in a temperature range from -55 to 125oC, respectively. It occupies around 0.014 mm2 of silicon area for a total power consumption of 5.9 W. Lastly, a few example Gm-C circuits are designed using GZTC technique: a single-ended resistor emulator, an impedance inverter, a first order and a second order filter. These circuits are simulated in a 130 nm CMOS commercial process, resulting improved thermal stability in the main performance parameters, in the range from 27 to 53 ppm/°C.A contínua miniaturização das tecnologias CMOS oferece maior capacidade de integração e, consequentemente, as variações de temperatura dentro de uma pastilha de silício têm se apresentado cada vez mais agressivas. Ademais, dependendo da aplicação, a temperatura ambiente a qual o CHIP está inserido pode variar. Dessa maneira, procedimentos para diminuir o impacto dessas variações no desempenho do circuito são imprescindíveis. Tais métodos devem ser incluídos em ambos fluxos de projeto CMOS, analógico e digital, de maneira que o desempenho do sistema se mantenha estável quando a temperatura oscilar. A ideia principal desta dissertação é propor uma metodologia de projeto CMOS analógico que possibilite circuitos com baixa dependência térmica. Como base fundamental desta metodologia, o efeito de coeficiente térmico nulo no ponto de polarização da corrente de dreno (ZTC) e da transcondutância (GZTC) do MOSFET são analisados e modelados. Tal modelamento é responsável por entregar ao projetista analógico um conjunto de equações que esclarecem como a temperatura influencia o comportamento do transistor e, portanto, o comportamento do circuito. Essas condições especiais de polarização são analisadas usando um modelo de MOSFET que é contínuo da inversão fraca para forte. Além disso, é mostrado que as duas condições ocorrem em inversão moderada para forte em qualquer processo CMOS. Algumas aplicações são projetadas usando a metodologia proposta: duas referências de corrente baseadas em ZTC, duas referências de tensão baseadas em ZTC, e quatro circuitos gm-C polarizados em GZTC. A primeira referência de corrente é uma Corrente de Referência CMOS Auto-Polarizada (ZSBCR), que gera uma referência de 5uA. Projetada em CMOS 180 nm, a referência opera com uma tensão de alimentação de 1.4 à 1.8 V, ocupando uma área em torno de 0:010mm2. Segundo as simulações, o circuito apresenta um coeficiente de temperatura efetivo (TCeff ) de 15 ppm/oC para -45 à +85 oC e uma sensibilidade à variação de processo de = = 4:5% incluindo efeitos de variabilidade dos tipos processo e descasamento local. A sensibilidade de linha encontrada nas simulações é de 1%=V . A segunda referência de corrente proposta é uma Corrente de Referência Sem Resistor Auto-Polarizada com Capacitor Chaveado (ZSCCR). O circuito é projetado também em 180 nm, resultando em uma corrente de referência de 5.88 A, para uma tensão de alimentação de 1.8 V, e ocupando uma área de 0:010mm2. Resultados de simulações mostram um TCeff de 60 ppm/oC para um intervalo de temperatura de -45 à +85 oC e um consumo de potência de 63 W. A primeira referência de tensão proposta é uma Referência de Tensão resistente à pertubações eletromagnéticas contendo apenas MOSFETs (EMIVR), a qual gera um valor de referência de 395 mV. O circuito é projetado no processo CMOS 130 nm, ocupando em torno de 0.0075 mm2 de área de silício, e consumindo apenas 10.3 W. Simulações pós-leiaute apresentam um TCeff de 146 ppm/oC, para um intervalo de temperatura de 55 à +125oC. Uma fonte EMI de 4 dBm (1 Vpp de amplitude) aplicada na alimentação do circuito, de acordo com o padrão Direct Power Injection (DPI), resulta em um máximo de desvio DC e ondulação Pico-à-Pico de -1.7 % e 35.8m Vpp, respectivamente. A segunda referência de tensão é uma Tensão de Referência baseada em diodo Schottky com 0.5V de alimentação (SBVR). Ela gera três saídas, cada uma utilizando MOSFETs com diferentes tensões de limiar (standard-VT , low-VT , e zero-VT ). Todos disponíveis no processo adotado CMOS 130 nm. Este projeto resulta em três diferentes voltages de referências: 312, 237, e 51 mV, apresentando um TCeff de 214, 372, e 953 ppm/oC no intervalo de temperatura de -55 à 125oC, respectivamente. O circuito ocupa em torno de 0.014 mm2, consumindo um total de 5.9 W. Por último, circuitos gm-C são projetados usando o conceito GZTC: um emulador de resistor, um inversor de impedância, um filtro de primeira ordem e um filtro de segunda ordem. Os circuitos também são simulados no processo CMOS 130 nm, resultando em uma melhora na estabilidade térmica dos seus principais parâmetros, indo de 27 à 53 ppm/°C

Wide Band Gap Devices and Their Application in Power Electronics

Power electronic systems have a great impact on modern society. Their applications target a more sustainable future by minimizing the negative impacts of industrialization on the environment, such as global warming effects and greenhouse gas emission. Power devices based on wide band gap (WBG) material have the potential to deliver a paradigm shift in regard to energy efficiency and working with respect to the devices based on mature silicon (Si). Gallium nitride (GaN) and silicon carbide (SiC) have been treated as one of the most promising WBG materials that allow the performance limits of matured Si switching devices to be significantly exceeded. WBG-based power devices enable fast switching with lower power losses at higher switching frequency and hence, allow the development of high power density and high efficiency power converters. This paper reviews popular SiC and GaN power devices, discusses the associated merits and challenges, and finally their applications in power electronics

Development of a Hybrid-Electric Aircraft Propulsion System Based on Silicon Carbide Triple Active Bridge Multiport Power Converter

Constrained by the low energy density of Lithium-ion batteries with all-electric aircraft propulsion, hybrid-electric aircraft propulsion drive becomes one of the most promising technologies in aviation electrification, especially for wide-body airplanes. In this thesis, a three-port triple active bridge (TAB) DC-DC converter is developed to manage the power flow between the turbo generator, battery, and the propulsion motor. The TAB converter is modeled based on the emerging Silicon Carbide (SiC) Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) modules operating at high switching frequency, so the size of the magnetic transformer can be significantly reduced. Different operation modes of this hybrid-electric propulsion drive based on the SiC TAB converter are modeled and simulated to replicate the takeoff mode, cruising mode, and regenerative charging mode of a typical flight profile. Additionally, soft switching is investigated for the TAB converter to further improve the efficiency and power density of the converter, and zero voltage switching is achieved at heavy load operating conditions. The results show that the proposed TAB converter is capable of achieving high efficiency during all stages of the flight profile

A novel active gate driver for improving SiC MOSFET switching trajectory

The trend in power electronic applications is to reach higher power density and higher efficiency. Currently, the wide band-gap devices such as silicon carbide MOSFET (SiC MOSFET) are of great interest because they can work at higher switching frequency with low losses. The increase of the switching speed in power devices leads to high power density systems. However, this can generate problems such as overshoots, oscillations, additional losses, and electromagnetic interference (EMI). In this paper, a novel active gate driver (AGD) for improving the SiC MOSFET switching trajectory with high performance is presented. The AGD is an open-loop control system and its principle is based on gate energy decrease with a gate resistance increment during the Miller plateau effect on gate-source voltage. The proposed AGD has been designed and validated through experimental tests for high-frequency operation. Moreover, an EMI discussion and a performance analysis were realized for the AGD. The results show that the AGD can reduce the overshoots, oscillations, and losses without compromising the EMI. In addition, the AGD can control the turn-on and turn-off transitions separately, and it is suitable for working with asymmetrical supplies required by SiC MOSFETs.Postprint (author's final draft

Trade-off between Losses and EMI Issues in Three-Phase SiC Inverters for Aircraft Applications

Power converters will only be effectively used in future aircrafts if they are compact, efficient and reliable. All these aspects can be improved by the use of disruptive technology such as the so-called Wide Bandgap (WBG) semiconductors made of Silicon Carbide (SiC) or Gallium Nitride (GaN). These components can switch much faster than their silicon counterpart, which can reduce converter losses and also decrease differential mode filter given the increase of switching frequency. However, such a fast commutation increases Electromagnetic Interference (EMI) issues in the converter and loads connected to it. This paper shows the approach developed at the French Institute of Technology (IRT) Saint-Exupery, in order to evaluate the trade-offs between losses and EMI issues of three-phase inverters used in future aircraft applications. Given the voltage DC bus of 540V, SiC MOSFETs are investigated and experimental results show the impact of these components on losses and EMI for different parameters

Modeling and Optimization Algorithm for SiC-based Three-phase Motor Drive System

More electric aircraft (MEA) and electrified aircraft propulsion (EAP) becomes the important topics in the area of transportation electrifications, expecting remarkable environmental and economic benefits. However, they bring the urgent challenges for the power electronics design since the new power architecture in the electrified aircraft requires many benchmark designs and comparisons. Also, a large number of power electronics converter designs with different specifications and system-level configurations need to be conducted in MEA and EAP, which demands huge design efforts and costs. Moreover, the long debugging and testing process increases the time to market because of gaps between the paper design and implementation. To address these issues, this dissertation covers the modeling and optimization algorithms for SiC-based three-phase motor drive systems in aviation applications. The improved models can help reduce the gaps between the paper design and implementation, and the implemented optimization algorithms can reduce the required execution time of the design program. The models related to magnetic core based inductors, geometry layouts, switching behaviors, device loss, and cooling design have been explored and improved, and several modeling techniques like analytical, numerical, and curve-fitting methods are applied. With the developed models, more physics characteristics of power electronics components are incorporated, and the design accuracy can be improved. To improve the design efficiency and to reduce the design time, optimization schemes for the filter design, device selection combined with cooling design, and system-level optimization are studied and implemented. For filter design, two optimization schemes including Ap based weight prediction and particle swarm optimization are adopted to reduce searching efforts. For device selection and related cooling design, a design iteration considering practical layouts and switching speed is proposed. For system-level optimization, the design algorithm enables the evaluation of different topologies, modulation schemes, switching frequencies, filter configurations, cooling methods, and paralleled converter structure. To reduce the execution time of system-level optimization, a switching function based simulation and waveform synthesis method are adopted. Furthermore, combined with the concept of design automation, software integrated with the developed models, optimization algorithms, and simulations is developed to enable visualization of the design configurations, database management, and design results

Coreless planar transformer for hard-switching applications

Leistungshalbleiter werden meist in schaltenden Anwendungen eingesetzt. Hartes Schalten ist hierfür ein gängiges und einfaches Funktionsprinzip, insbesondere bei induktiven Lasten. Hier können durch Verkürzung der Übergangsdauer zwischen Spannung und Strom die Schaltverluste reduziert werden. Die Nachteile schnellerer Übergänge in hart schaltenden Anwendungen sind in der Regel höhere Überschwingungen und außerdem die Erzeugung von elektromagnetischen Störungen. Die maximale Überspannung wird hierbei durch die Sperrspannung des Halbleiters begrenzt. Ein gängiger Ansatz zur Reduzierung der Überspannungen für einen Leistungshalbleiter ist die Minimierung der Induktivität im Leistungspfad. Ein in Reihe mit den Leistungsanschlüssen des Halbleiters geschalteter Transformator kann jedoch für verschiedene Anwendungen von Vorteil sein. Insbesondere die hohen Stromgradienten bei schnellen, harten Schaltvorgängen sorgt für eine hohe, und somit gut nutzbare Ausgangsspannung des Transformators. In dieser Arbeit wird ein neues Design eines kernlosen Planartransformators vorgestellt. Eine hohe magnetische Kopplung und ein einstellbares Übersetzungsverhältnis sowie eine besonders hohe Bandbreite sorgen dafür, dass die Induktivität in Reihe mit dem Halbleiter minimal gehalten werden kann. Der zweischichtige Aufbau ist zudem für verschiedene Substrate, insbesondere Leiterplatten, geeignet. Ein bis zur ersten Resonanzfrequenz gültiges Simulationsmodell des neuen Übertragerdesigns wurde erstellt und verifiziert. Die Anwendung, für die der Übertrager in dieser Arbeit hauptsächlich eingesetzt wird, ist das induktive Feed-Forward-Verfahren. Diese Methode zur Steuerung von Leistungshalbleitern beschleunigt das Umschalten in hart schaltenden Anwendungen. Die Methode wird analysiert und Verbesserungen für eine Auswahl von Leistungshalbleiter-Designs werden vorgeschlagen und verifiziert. Weiterhin wird die Ansteuerungsmethode modifiziert, um symmetrische Stromgradienten in parallel geschalteten Leistungshalbleitern zu erreichen. Außerdem wird der Übertrager vergleichbar zu einer Rogowski-Spule als Stromsensor genutzt, um die hohen Stromgradienten beim Schalten zu charakterisieren. Es wird gezeigt, dass durch verpolung der Sekundärwicklung das induktive Feed-Forward-Verfahren zur Verlangsamung des Schaltvorganges eingesetzt werden kann. In der letzten in dieser Arbeit vorgestellten Anwendung wird der Übertrager zur Erzeugung einer isolierten Versorgungsspannung für die Gate Ansteuerung eingesetzt. Die Anwendung ist besonders vorteilhaft, wenn eine negative Versorgungsspannung erforderlich ist, z.B. aufgrund einer niedrigen Schwellspannung

Modeling, Measurement and Mitigation of Fast Switching Issues in Voltage Source Inverters

Wide-bandgap devices are enjoying wider adoption across the power electronics industry for their superior properties and the resulting opportunities for higher efficiency and power density. However, various issues arise due to the faster switching speed, including switching transient voltage overshoot, unstable oscillation, gate driving and evaluation difficulty, measurement and monitoring challenge, and potential load insulation degradation. This dissertation first sets out to model and understand the switching transient voltage overshoots. Unique oscillation patterns and features of the turn-on and turn-off overvoltage are discovered and analyzed, which provides new insights into the switching transient. During the experimental characterization, a new unstable oscillation pattern is found during the trench MOSFET\u27s turn-off transient. The MOSFET channel may be falsely turned back on, resulting in severe oscillation and possible loss of control. Time-domain and large-signal analytical models are established, which reveals the negative impact of common-source inductances and unconventional capacitance curve of trench MOSFET. Besides the devices themselves, another determining part in their switching transient behavior is the gate driver. A programmable gate driver platform is proposed to readily adapt to different power semiconductors and driving schemes, which can greatly facilitate the evaluation and comparison of different devices and driving schemes. The faster switching speed of wide-bandgap devices also requires more demanding measurement and monitoring solutions. A novel combinational Rogowski coil concept is proposed, which leverages the self-integrating feature to further increase the bandwidth. Prototypes achieved more than 300 MHz bandwidth, while keeping the cross-sectional area less than 2.5 mm$^2$. Finally, the very high voltage slew rate of wide-bandgap devices may negatively impact the motor load insulation. Attempting to fully utilize the higher switching frequency capability, sinewave and $dv/dt$ filters are compared. It is shown that sinewave filters can achieve higher efficiency and power density than $dv/dt$ filters, especially for high frequency applications

Design and Validation of A High-Power, High Density All Silicon Carbide Three-Level Inverter

Transportation electrification is clearly the road toward the future. Compared to internal combustion engine, the electrified vehicle has less carbon-dioxide emission, less maintenance costs and less operation costs. It also offers higher efficiency and safety margin. More importantly, it relieves human’s dependence on conventional fossil energy. In the electrification progress, the revolution of electric traction drive systems is one of the most important milestone. The traction system should keep high efficiency to avoid performance reduction. Moreover, the motor drive should be designed within limited space without sacrificing output power rating. Based on the road map from US Drive Electrical and Electronics Technical Team, US Department of Energy, a gap is still there between roadmap target and the state-of-art. To fill the gap, this dissertation performs a systematic research in motor drive system for traction inverters. This paper starts from optimal theoretical design of power converters by using loss model and real-time simulation system. Based on optimal paper design, hardware design is implemented. The component design for converter, such as the laminated busbar, are the focus in this dissertation. The optimized busbar structure can effectively reduce stray inductance in the current-commutation loop, reducing switching overshoots of power modules and increasing semiconductor reliability. The system-level design and trade-off is also analyzed and illustrated by using a 250kW three-level T-type neutral-point clamped converter. The design has reached high efficiency and high-power density. The converter system is also evaluated through comprehensive tests, such as double-pulse tests and continuous tests. The test setup, test condition and test result analysis are discussed in the dissertation. In the end, the dissertation also proposed an improved impedance characterization method for components parasitic inductance measurement in traction drive systems, such as laminated busbar, power module and capacitors. The characterization shares better accuracy and can be customized for device under test with any geometry