이동통신 기기에 적합한 재구성이 가능한 다중대역 선형 CMOS 전력증폭기에 관한 연구

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2015. 2. 권영우.In this Dissertation, a study on multiband reconfigurable linear CMOS power amplifier (PA) is performed. Since a larger number of frequency bands is allocated for 3G/4G mobile communication standards nowadays, handset PAs are required to support the ever-increasing number of frequency bands. With the advent of high-speed wireless data transmission, handset PAs are also demanded to perform linear power amplification under the wide-band signal condition. Even though the CMOS technology has cost and size benefits, however, designing a watt-level linear CMOS PA is a challenging issue due to low breakdown voltage and nonlinear nature of the CMOS device. To resolve the issues above, this study presents two methods suitable for multiband (MB) linear CMOS PA: a reconfigurable MB matching structure and a linearization technique. The proposed MB structure shares a PA core to reduce the cost and size, and contains the power- and frequency-reconfigurable matching networks as well as the output path-selection function. Thus, it can perform the MB operation requiring multiple frequency bands and target output powers. The reconfiguration mechanism is quantitatively analyzed and experimentally demonstrated. The fabricated tri-band reconfigurable 3G UMTS PA using an InGaP/GaAs heterojunction bipolar transistor (HBT) process for practical handset application showed minimal efficiency degradation of less than 2% by multi-banding, compared with a single-band reference PA. For linearization of a CMOS PA, a phase-based linearization technique is presented. Since the PA nonlinearity is determined by the dynamic AM-AM and AM-PM, the two distortions should simultaneously be considered in linearization. Contrary to the previous works which have focused on the correction of AM-AM distortion by providing an envelope-dependent gate-bias, this work proposes an AM-PM linearizer using a varactor and an envelope-reshaping circuit. This linearizer helps the PA recover AM-AM distortion as well. To validate the usefulness of the proposed linearizer, 1.88 GHz and 0.9 GHz stacked-FET PAs using a 0.32-μm silicon-on-insulator (SOI) CMOS process were designed and fabricated. Measurement results showed that the fabricated 1.88 / 0.9 GHz linear CMOS PAs achieved linear efficiencies (meeting –39 dBc W-CDMA ACLR) of higher than 44 / 49%. Furthermore, a single-chain MB linear CMOS PA was implemented based on the proposed MB reconfiguration and linearization techniques. The fabricated MB PA, which has two outputs and covers five popular uplink UMTS/LTE bands (Band 1/2/4/5/8: 824 ~ 1980 MHz), showed minimal efficiency degradation (< 3.3%) compared to the single-band dedicated CMOS PA with W-CDMA efficiencies in excess of 40.7%. Finally, the signal-bandwidth limiting effect of the envelope-based linear CMOS PA is discussed and a solution is proposed. Due to the time delay during envelope-detection and shaping, a timing mismatch between the incoming RF signal and envelope-reshaped signal occurs, thus resulting in no linearization effect under wide-band signal (LTE 20 MHz or more) conditions. To resolve the problem, a group delay circuit with a compact size is employed and thus the linearization effect of the proposed phase-based linearizer is maintained up to 40 MHz LTE bandwidth.Abstract i Contents iii List of Tables vi List of Figures vii 1. Introduction 1 1.1 Motivation 1 1.2 Multiband PA Structure 4 1.3 Linearization of CMOS PA 6 1.4 Dissertation Organization 7 1.5 References 9 2. A Multiband Reconfigurable Power Amplifier for 3G UMTS Handset Applications 10 2.1 Introduction 10 2.2 Operation Principle of the Reconfigurable Output Matching Network 12 2.2.1 Power Reconfigurable Network (PRN) 14 2.2.2 Frequency Reconfigurable Network (FRN) 17 2.2.3 Path Selection Network (PSN) 20 2.2.4 Experimental Validation of the PRN and FRN 24 2.3 Fabrication and Measurement of a MB UMTS Reconfigurable PA 26 2.3.1 Design 26 2.3.2 Measurement 31 2.4 Summary 37 2.5 References 38 3. Linearization of CMOS Power Amplifier and Its Multiband Application 41 3.1 Introduction 41 3.2 Linearization of CMOS PAs: Prior Arts 43 3.3 Harmonic Termination 46 3.3.1 Operation Analysis 47 3.3.2 Experimental Validation 52 3.4 Control of Gate Bias Modulation Effect 54 3.4.1 Analysis 54 3.4.2 Experimental Validation 60 3.5 Proposed Linearization #1: Hybrid Bias 67 3.6 Proposed Linearization #2: Phase Injection 71 3.6.1 Motivation 71 3.6.2 Phase (Capacitance) Injection 72 3.7 Linear CMOS PA Design 75 3.7.1 Baseline PA Design 76 3.7.2 Linearizer Design 78 3.7.3 Fabrication 82 3.8 Measurement Results 83 3.8.1 CW Measurement 83 3.8.2 W-CDMA Measurement 84 3.8.3 LTE Measurement 87 3.9 A Single-Chain MB Reconfigurable Linear PA in SOI CMOS 90 3.9.1 MB Linear CMOS PA: Design 90 3.9.2 MB Linear CMOS PA: Measurement 94 3.10 Summary 99 3.11 References 100 4. Linearization of CMOS Power Amplifier Convering Wideband Signal 105 4.1 Introduction 105 4.2 Bandwidth Limitation of Envelope-Based Linearizers 106 4.2.1 Analysis 106 4.2.2 Delay Correction 110 4.2.3 Feedforward Envelope-Detection Structure with a Delay T/L 114 4.3 Group Delay Circuit 117 4.3.1 Positive GDC versus Negative GDC 117 4.3.2 Left-Handed T/L-Based GDC 119 4.4 Fabrication and Measurement 122 4.4.1 GDC Measurement 123 4.4.2 LTE Measurement 124 4.5 Summary 127 4.6 References 128 5. Conclusions 130 5.1 Research Summary 130 5.2 Future Works 132 Abstract in Korean 133 Publications 135Docto

고효율 고전압 포락선 추적 전력 증폭기에 관한 연구

학위논문 (박사)-- 서울대학교 대학원 공과대학 전기·컴퓨터공학부, 2017. 8. 서광석.In this dissertation, two advanced techniques to solve system issues in envelope tracking power amplifier (ET PA) is presented. First of all, a two-stage broadband CMOS stacked FET RF power amplifier (PA) with a reconfigurable interstage matching network is developed for wideband envelope tracking (ET). The proposed RF PA is designed based on Class-J mode of operation, where the output matching is realizedwith a two-section low-pass matching network. To overcome the bandwidth (BW) limitation from the high- interstage impedance, a reconfigurable matching network is proposed, allowing a triple frequency mode of operation using two RF switches. The proposed RF PA is fabricated in a 0.32-μm silicon-on-insulator CMOS process and shows continuous wave (CW) power-added efficiencies (PAEs) higher than 60% from 0.65 to 1.03 GHz with a peak PAE of 69.2% at 0.85 GHz. The complete ET PA system performance is demonstrated using the envelope amplifier fabricated on the same process. When measured using a 20-MHz BW long-term evolution signal, the overall system PAE of the ET PA is higher than 40% from 0.65 to 0.97 GHz while evolved universal terrestrial radio access (E-UTRA) adjacent channel leakage ratios (ACLRs) are better than –33 dBc across the entire BW after memoryless digital pre-distortion. To our knowledge, this study represents the highest overall system performance in terms of PAE and BW among the published broadband ET PAs, including GaAs HBT and SiGe BiCMOS. Second, a high-efficiency gallium-nitride (GaN) envelope amplifier (EA) is developed using class-E2 architecture for wideband LTE applications. The proposed EA consists of a class-E2 resonant converter which output voltage is controlled by a frequency modulator. With a pulse frequency modulation (PFM) signal, the output of the converter can achieve a linear response to the input wideband envelope signal. The frequency modulator with a cross-coupled oscillator and a driver using stacked-FETs structure is fabricated using 0.28-μm SOI CMOS process. The class-E2 converter and PA have been implemented using a commercial GaN device. The envelope amplifier (EA) achieves 74.7% efficiency into a 50 Ω load for a 20-MHz BW LTE signal with a 7.5 dB peak-to-average power ratio (PAPR) and there is no efficiency degradation as the LTE signal bandwidth increases to 160-MHz. The ET transmitter system demonstrated using the CMOS and GaN shows an overall system efficiency of 47.4% at 35.4 dBm with 20-MHz BW LTE signal centered at 3.5 GHz. The measured E-UTRA ACLR of ET PA is –33.8 dBc at 34.4 dBm output power before linearization and –42.9 dBc at the same output power after memory digital pre-destination (DPD). When tested using 80-MHz BW LTE signal, the overall system PAE reaches 46.5% at 35.3 dBm output power and E-UTRA ACLR was measured by –31.5 dBc at 34.4 dBm output power. A wideband performance is characterized using various bandwidth LTE signals which shows only 2.3 dB ACLR degradation without PAE degradation as the signal bandwidth is increased from 20- to 80-MHz. The proposed method is a first demonstration of GaN EA cover 160-MHz BW LTE signals and overcomes the efficiency degradation of the conventional EA as the signal bandwidth increase.Abstract Contents List of Tables List of Figures 1. Introduction 1.1 Motivation 1.2 Dissertation organization 2. Broadband CMOS Stacked RF Power Amplifier Using Reconfigurable Interstage Network for Wideband Envelope Tracking 2.1 Introduction 2.2 Two-stage broadband class-J PA 2.2.1 Review of the class-J PA 2.2.2 BW limitation in multi-stage PAs and proposed solution 2.2.3 Output matching netwok 2.2.4 Reconfigurable interstage matching network 2.3 Design and implementation of ET PA 2.3.1 Power amplifier design 2.3.2 Envelope amplifier design 2.4 Measurement results 2.5 Conclusions 2.6 References 3. A GaN Envelope Amplifier using Class-E2 Architecture for Wideband Envelope Tracking Applications 3.1 Introduction 3.2 Operation principle of the proposed envelope amplifier 3.2.1 Operation principle of class-E inverter and rectifier 3.2.2 Operation comparison of class-E2 between PWM and PFM 3.3 Detailed ET PA design and simulation 3.3.1 Envelope amplifier design using current-starved VCO (CSVCO) 3.3.2 Envelope amplifier design using cross-coupled VCO (CCVCO) 3.4 Measurement results 3.5 Conclusions 3.6 References 4. Conclusions and Future Works Abstract in KoreanDocto

펄스에 의한 동적 부하 변조 기술을 이용한 고효율 선형 송신기에 관한 연구

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2016. 8. 서광석.STRONG push for longer battery life time and growing thermal concerns for the modern 3G/4G mobile terminals lead to an ever-growing need for higher efficiencies from the handset power amplifiers (PAs). Furthermore, as the modulation signal bandwidth is increased and more complex modulation schemes are introduced for higher data rate, the peak-to-average power ratio (PAPR) of signals increases and the PA requires more power back-off to meet the stringent linearity requirement. Therefore, the PA design has to address the challenging task of enhancing the efficiencies in the back-off power levels. In this dissertation, dynamic load modulation (DLM) technique is investigated to boost the efficiency of a PA in the back-off output power level. This technique increases the efficiency by adjusting the PA load impedance according to the magnitude of the envelope signal. It can be categorized into two types, continuous and discrete types. Continuous-type DLM PA changes load impedance continuously by changing the capacitance of varactors used in the load matching circuit. Although the continuous modulation of the load impedance may result in significant efficiency enhancement, difficulties on integration of varactors and complexities on linearization of the PA make it difficult to be applied to the handset PA applications. Discrete-type DLM PA switches the load impedance from one value to another using RF switches. This type has the advantage in the aspect of ease of integration and simplicity in linearization compared to the continuous-type DLM PA, which make it more suited to the handset PA applications. However, the overall efficiency enhancement is quite limited since the PA does not always operate under the optimal load conditions. To overcome the limitation of the existing DLM techniques, a new method of DLM, called pulsed dynamic load modulation (PDLM), is proposed to operate the PA near the optimum impedance across a continuous back-off power range while still benefiting from the advantages offered by the discrete-type DLM PA. PDLM PA combines the concept of Class-S PA with 1-bit discrete load switching. Analytical calculation using simplified equivalent model is well matched with simulation results. To prove the proposed concept, it is implemented by designing and fabricating a prototype PDLM PA at 837 MHz using a 0.32-μm silicon-on-insulator (SOI) CMOS process. The experimental results show the overall PAE improvement for high-PAPR signals such as LTE signals. Several issues caused by the PDLM technique are also discussed such as imperfect pulse tone termination effect and output noise spectrum due to pulse tones. Improving methods are proposed through the further analysis and evaluation. The proposed PA is compared to the envelope tracking (ET) PA which is commonly used to boost efficiency at the back-off output power. Since the proposed concept is realized with low-power control circuits unlike envelope tracking, which requires high-power circuits such as dc-dc converters and linear amplifiers, the PDLM PA concept of this work can provide a potential solution for high-efficiency PAs for the future mobile terminals using wideband modulation signals.Chapter 1. Introduction 1 Chapter 2. Dynamic Load Modulation Technique 8 2.1 Introduction 8 2.2 Continuous-type dynamic load modulation PA 9 2.3 Discrete-type dynamic load modulation PA 14 2.4 Implementation example 15 2.4.1 DLM PA Structure 16 2.4.2 Linearization 23 2.4.3 Experimental Results 25 2.4.4 Conclusion 31 2.5 Limitations 32 2.6 References 33 Chapter 3. A Pulsed Dynamic Load Modulation Technique for High-Efficiency Linear Transmitters 36 3.1 Introduction 36 3.2 Operation Principle of the PDLM PA 38 3.2.1 Concept of the PDLM PA 38 3.2.2 Theoretical Analysis of the PDLM PA 41 3.3 Circuit Design 47 3.3.1 2 stage CMOS PA design 49 3.3.2 High power RF switch design 59 3.3.3 PWM signal generator and switch driver 61 3.4 Experimental Results 63 3.5 Conclusion 76 3.6 References 77 Chapter 4. Discussions 83 4.1 Operation bandwidth of the PDLM PA 83 4.2 Spectral noise reduction method 87 4.3 References 91 Chapter 5. Conclusions 94 5.1 Research Summary 94 5.2 Future Works 95 Abstract in Korean 97 Publications 99Docto

RF CMOS switch design methodologies for multiband transceiver applications

Multimode multiband connectivity has become a de-facto requirement for smartphones with 3G WCDMA/4G LTE applications. In transceivers, multiband operation is achieved by selecting an output from two or more signal path targeting for a specific frequency range in parallel or by using switched capacitor/inductor. In this paper, design methodology of 280nm CMOS switch is presented. Design optimization of RF CMOS switch is presented which is deciding proper selection of CMOS transistor parameters and switch size as per external circuit parameters. The CMOS switch of a 5-transistor stack with W/L=1200µm/280nm provides insertion loss 14dB. The switches designed when implemented in a multiband power amplifier (PA) exhibits 36dB gain at 1900MHz high-band and 34.5dB gain at 900MHz low-band with 27.5dBm peak power at both bands. The switch design methodologies presented in this paper should be of use in designing various blocks in emerging multiband transceiver applications

Concurrent Quad-band Low Noise Amplifier (QB-LNA) using Multisection Impedance Transformer

A quad-band low noise amplifier (QB-LNA) based on multisection impedance transformer designed and evaluated in this research. As a novelty, a multisection impedance transformer was used to produce QB-LNA. A multisection impedance transformer is used as input and output impedance matching because it has higher stability, large Q factor, and low noise than lumpedcomponent.The QB-LNA was designed on FR4 microstrip substrate with er= 4.4, thickness h=0.8 mm, and tan d= 0.026. The proposed QB-LNA was designed and analyzed by Advanced Design System (ADS).The simulation has shown that QB-LNA achieves gain (S21) of 22.91 dB, 16.5 dB,  11.18 dB, and 7.25 dB at 0.92 GHz, 1.84 GHz, 2.61 GHz, and 3.54 GHz, respectively.The QB-LNA obtainreturn loss (S11) of -21.28 dB, -31.87 dB,  -28.08 dB, and -30.85 dB at 0.92 GHz, 1.84 GHz, 2.61 GHz, and 3.54 GHz, respectively. It also achieves a noise figure (nf) of 2.35 dB, 2.13 dB, 2.56 dB, and 3.55 dB at 0.92 GHz, 1.84 GHz, 2.61 GHz, and 3.54 GHz, respectively. This research also has shown that the figure of merit (FoM) of the proposed QB-LNA is higher than that of another multiband LNA

A 2.4 GHz CMOS class-F power amplifier with reconfigurable load-impedance matching

© 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.A novel reconfigurable CMOS class-F power amplifier (PA) at 2.4 GHz is proposed in this paper. It is able to match the output load variations mainly due to the effect of hand and head on a mobile phone. The effect of load variation on power-added efficiency (PAE), output power, and distortion is compensated by reconfiguring the output network using an impedance tuner. The tuner controls the output matching at fundamental frequency without affecting the class-F harmonic tuning up to 3rd harmonic. To the best of our knowledge, this is the first design of a CMOS class-F PA addressed to compensate the effect of load variation. Measurement results for 50 ohm load impedance show a maximum PAE of 26% and maximum output power of 19.2 dBm. The measured total harmonic distortion is 4.9%. Measurement results for load values other than 50 ohm show that PAE increases from 6.5% (not-tuned PA) up to 19.9% (tuned PA) with the same output power (19.2 dBm). Tuning also reduces the adjacent-channel leakage ratio by 5 dB and the spectral regrowth of a Wi-Fi signal at the PA output. The size of the fabricated chip is 1.6 mm × 1.6 mm.Peer ReviewedPostprint (author's final draft

Reconfigurable Antennas

In this new book, we present a collection of the advanced developments in reconfigurable antennas and metasurfaces. It begins with a review of reconfigurability technologies, and proceeds to the presentation of a series of reconfigurable antennas, UWB MIMO antennas and reconfigurable arrays. Then, reconfigurable metasurfaces are introduced and the latest advances are presented and discussed

Saw-Less radio receivers in CMOS

Smartphones play an essential role in our daily life. Connected to the internet, we can easily keep in touch with family and friends, even if far away, while ever more apps serve us in numerous ways. To support all of this, higher data rates are needed for ever more wireless users, leading to a very crowded radio frequency spectrum. To achieve high spectrum efficiency while reducing unwanted interference, high-quality band-pass filters are needed. Piezo-electrical Surface Acoustic Wave (SAW) filters are conventionally used for this purpose, but such filters need a dedicated design for each new band, are relatively bulky and also costly compared to integrated circuit chips. Instead, we would like to integrate the filters as part of the entire wireless transceiver with digital smartphone hardware on CMOS chips. The research described in this thesis targets this goal. It has recently been shown that N-path filters based on passive switched-RC circuits can realize high-quality band-select filters on CMOS chips, where the center frequency of the filter is widely tunable by the switching-frequency. As CMOS downscaling following Moore’s law brings us lower clock-switching power, lower switch on-resistance and more compact metal-to-metal capacitors, N-path filters look promising. This thesis targets SAW-less wireless receiver design, exploiting N-path filters. As SAW-filters are extremely linear and selective, it is very challenging to approximate this performance with CMOS N-path filters. The research in this thesis proposes and explores several techniques for extending the linearity and enhancing the selectivity of N-path switched-RC filters and mixers, and explores their application in CMOS receiver chip designs. First the state-of-the-art in N-path filters and mixer-first receivers is reviewed. The requirements on the main receiver path are examined in case SAW-filters are removed or replaced by wideband circulators. The feasibility of a SAW-less Frequency Division Duplex (FDD) radio receiver is explored, targeting extreme linearity and compression Irequirements. A bottom-plate mixing technique with switch sharing is proposed. It improves linearity by keeping both the gate-source and gate-drain voltage swing of the MOSFET-switches rather constant, while halving the switch resistance to reduce voltage swings. A new N-path switch-RC filter stage with floating capacitors and bottom-plate mixer-switches is proposed to achieve very high linearity and a second-order voltage-domain RF-bandpass filter around the LO frequency. Extra out-of-band (OOB) rejection is implemented combined with V-I conversion and zero-IF frequency down-conversion in a second cross-coupled switch-RC N-path stage. It offers a low-ohmic high-linearity current path for out-of-band interferers. A prototype chip fabricated in a 28 nm CMOS technology achieves an in-band IIP3 of +10 dBm , IIP2 of +42 dBm, out-of-band IIP3 of +44 dBm, IIP2 of +90 dBm and blocker 1-dB gain-compression point of +13 dBm for a blocker frequency offset of 80 MHz. At this offset frequency, the measured desensitization is only 0.6 dB for a 0-dBm blocker, and 3.5 dB for a 10-dBm blocker at 0.7 GHz operating frequency (i.e. 6 and 9 dB blocker noise figure). The chip consumes 38-96 mW for operating frequencies of 0.1-2 GHz and occupies an active area of 0.49 mm2. Next, targeting to cover all frequency bands up to 6 GHz and achieving a noise figure lower than 3 dB, a mixer-first receiver with enhanced selectivity and high dynamic range is proposed. Capacitive negative feedback across the baseband amplifier serves as a blocker bypassing path, while an extra capacitive positive feedback path offers further blocker rejection. This combination of feedback paths synthesizes a complex pole pair at the input of the baseband amplifier, which is up-converted to the RF port to obtain steeper RF-bandpass filter roll-off than the conventional up-converted real pole and reduced distortion. This thesis explains the circuit principle and analyzes receiver performance. A prototype chip fabricated in 45 nm Partially Depleted Silicon on Insulator (PDSOI) technology achieves high linearity (in-band IIP3 of +3 dBm, IIP2 of +56 dBm, out-of-band IIP3 = +39 dBm, IIP2 = +88 dB) combined with sub-3 dB noise figure. Desensitization due to a 0-dBm blocker is only 2.2 dB at 1.4 GHz operating frequency. IIFinally, to demonstrate the performance of the implemented blocker-tolerant receiver chip designs, a test setup with a real mobile phone is built to verify the sensitivity of the receiver chip for different practical blocking scenarios