A study of Radiation-Tolerant Voltage-Controlled Oscillators designs in 65 nm bulk and 28 nm FDSOI CMOS technologies

Phase-locked loop (PLL) systems are widely employed in integrated circuits for space analog devices and communications systems that operate in radiation environments, where significant perturbations, especially in terms of phase noise, can be generated due to radiation particles. Among all the blocks that form a PLL system, previous research suggests the voltage-controlled oscillator (VCO) is one of the most critical components in terms of radiation tolerance and electric performance. Ring oscillators (ROs) and LC-tank VCOs have been commonly employed in high-performance PLLs. Nevertheless, both structures have drawbacks including a limited tuning range, high sensitivity to phase noise, limited radiation tolerance, and large design areas. In order to fulfill these high-performance requirements, a current-model logic (CML) based RO-VCO is presented as a possible solution capable of reducing the limitations of the commonly used structures and exploiting their advantages. The proposed hybrid VCO model includes passive components in its design which are the key parameters that define oscillation frequency of this structure. This tunable oscillator has been designed and tested in 65nm Bulk and 28 nm Fully depleted silicon-on-insulator (FDSOI) CMOS technologies The 65nm testchip was designed to compare the behavior of the proposed CML VCO with a current-starved RO and a radiation hardened by design (RHBD) LC-tank VCO in terms of tuning range, phase noise, Single event effect (SEE) sensitivity and design area. Simulations were carried out by applying a double exponential current pulse into different sensitive nodes of the three VCOs. In addition, SEE tests were conducted using pulsed laser experiments. Simulation and test results show that a CML VCO can effectively overcome the limitations presented by a RO-VCO and LC-tank VCO, achieving a wide range of tuning, and low sensitivity to noise and SEEs without the need for a large cross-section. Further studies of the proposed CML VCO were done on 28nm FDSOI in order to reduce the leakage current and increase the switching speed. the same current-starved VCO and CML VCO were implemented on this testchip, and simulations were performed by injecting a double exponential current pulse energy into the previously defined sensitive nodes. The results show SEE sensitivity improvement without narrowing the tuning range or affecting the phase noise response

Voltage controlled oscillator for mm-wave radio systems

Abstract. The advancement in silicon technology has accelerated the development of integrated millimeter-wave transceiver systems operating up to 100 GHz with sophisticated functionality at a reduced consumer cost. Due to the progress in the field of signal processing, frequency modulated continuous wave (FMCW) radar has become common in recent years. A high-performance local oscillator (LO) is required to generate reference signals utilized in these millimeter-wave radar transceivers. To accomplish this, novel design techniques in fundamental voltage controlled oscillators (VCO) are necessary to achieve low phase noise, wide frequency tuning range, and good power efficiency. Although integrated VCOs have been studied for decades, as we move higher in the radio frequency spectrum, there are new trade-offs in the performance parameters that require further characterization. The work described in this thesis aims to design a fully integrated fundamental VCO targeting to 150 GHz, i.e., D-Band. The purpose is to observe and analyze the design limitations at these high frequencies and their corresponding trade-offs during the design procedure. The topology selected for this study is the cross-coupled LC tank VCO. For the study, two design topologies were considered: a conventional cross-coupled LC tank VCO and an inductive divider cross-coupled LC tank VCO. The conventional LC tank VCO yields better performance in terms of phase noise and tuning range. It is observed that the VCO is highly sensitive to parasitic contributions by the transistors, and the layout interconnects, thus limiting the targeted frequency range. The dimensions of the LC tank and the transistors are selected carefully. Moreover, the VCO performance is limited by the low Q factor of the LC tank governed by the varactor that is degrading the phase noise performance and the tuning range, respectively. The output buffer loaded capacitance and the core power consumption of the VCO are optimized. The layout is drawn carefully with strategies to minimize the parasitic effects. Considering all the design challenges, a 126 GHz VCO with a tuning range of 3.9% is designed. It achieves FOMT (Figure-of-merit) of -172 dBc/Hz, and phase noise of -99.14 dBc/Hz at 10 MHz offset, Core power consumption is 8.9 mW from a 1.2 V supply. Just falling short of the targeted frequency, the design is suitable for FMCW radar applications for future technologies. The design was done using Silicon-on-Insulator (SOI) CMOS technology

Analysis and Design of Silicon based Integrated Circuits for Radio Frequency Identification and Ranging Systems at 24GHz and 60GHz Frequency Bands

This scientific research work presents the analysis and design of radio frequency (RF) integrated circuits (ICs) designed for two cooperative RF identification (RFID) proof of concept systems. The first system concept is based on localizable and sensor-enabled superregenerative transponders (SRTs) interrogated using a 24GHz linear frequency modulated continuous wave (LFMCW) secondary radar. The second system concept focuses on low power components for a 60GHz continuous wave (CW) integrated single antenna frontend for interrogating close range passive backscatter transponders (PBTs). In the 24GHz localizable SRT based system, a LFMCW interrogating radar sends a RF chirp signal to interrogate SRTs based on custom superregenerative amplifier (SRA) ICs. The SRTs receive the chirp and transmit it back with phase coherent amplification. The distance to the SRTs are then estimated using the round trip time of flight method. Joint data transfer from the SRT to the interrogator is enabled by a novel SRA quench frequency shift keying (SQ-FSK) based low data rate simplex communication. The SRTs are also designed to be roll invariant using bandwidth enhanced microstrip patch antennas. Theoretical analysis is done to derive expressions as a function of system parameters including the minimum SRA gain required for attaining a defined range and equations for the maximum number of symbols that can be transmitted in data transfer mode. Analysis of the dependency of quench pulse characteristics during data transfer shows that the duty cycle has to be varied while keeping the on-time constant to reduce ranging errors. Also the worsening of ranging precision at longer distances is predicted based on the non-idealities resulting from LFMCWchirp quantization due to SRT characteristics and is corroborated by system level measurements. In order to prove the system concept and study the semiconductor technology dependent factors, variants of 24GHz SRA ICs are designed in a 130nm silicon germanium (SiGe) bipolar complementary metal oxide technology (BiCMOS) and a partially depleted silicon on insulator (SOI) technology. Among the SRA ICs designed, the SiGe-BiCMOS ICs feature a novel quench pulse shaping concept to simultaneously improve the output power and minimum detectable input power. A direct antenna drive SRA IC based on a novel stacked transistor cross-coupled oscillator topology employing this concept exhibit one of the best reported combinations of minimum detected input power level of −100 dBm and output power level of 5.6 dBm, post wirebonding. The SiGe stacked transistor with base feedback capacitance topology employed in this design is analyzed to derive parameters including the SRA loop gain for design optimization. Other theoretical contributions include the analysis of the novel integrated quench pulse shaping circuit and formulas derived for output voltage swing taking bondwire losses into account. Another SiGe design variant is the buffered antenna drive SRA IC having a measured minimum detected input power level better than −80 dBm, and an output power level greater than 3.2 dBm after wirebonding. The two inputs and outputs of this IC also enables the design of roll invariant SRTs. Laboratory based ranging experiments done to test the concepts and theoretical considerations show a maximum measured distance of 77m while transferring data at the rate of 0.5 symbols per second using SQ-FSK. For distances less than 10m, the characterized accuracy is better than 11 cm and the precision is better than 2.4 cm. The combination of the maximum range, precision and accuracy are one of the best reported among similar works in literature to the author’s knowledge. In the 60GHz close range CW interrogator based system, the RF frontend transmits a continuous wave signal through the transmit path of a quasi circulator (QC) interfaced to an antenna to interrogate a PBT. The backscatter is received using the same antenna interfaced to the QC. The received signal is then amplified and downconverted for further processing. To prove this concept, two optimized QC ICs and a downconversion mixer IC are designed in a 22nm fully depleted SOI technology. The first QC is the transmission lines based QC which consumes a power of 5.4mW, operates at a frequency range from 56GHz to 64GHz and occupies an area of 0.49mm2. The transmit path loss is 5.7 dB, receive path gain is 2 dB and the tunable transmit path to receive path isolation is between 20 dB and 32 dB. The second QC is based on lumped elements, and operates in a relatively narrow bandwidth from 59.6GHz to 61.5GHz, has a gain of 8.5 dB and provides a tunable isolation better than 20 dB between the transmit and receive paths. This QC design also occupies a small area of 0.34mm² while consuming 13.2mW power. The downconversion is realized using a novel folded switching stage down conversion mixer (FSSDM) topology optimized to achieve one of the best reported combination of maximum voltage conversion gain of 21.5 dB, a factor of 2.5 higher than reported state-of-the-art results, and low power consumption of 5.25mW. The design also employs a unique back-gate tunable intermediate frequency output stage using which a gain tuning range of 5.5 dB is attained. Theoretical analysis of the FSSDM topology is performed and equations for the RF input stage transconductance, bandwidth, voltage conversion gain and gain tuning are derived. A feasibility study for the components of the 60GHz integrated single antenna interrogator frontend is also performed using PBTs to prove the system design concept.:1 Introduction 1 1.1 Motivation and Related Work . . . . . . . . . . . . . . . . . . . . . 1 1.2 Scope and Functional Specifications . . . . . . . . . . . . . . . . . 4 1.3 Objectives and Structure . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Features and Fundamentals of RFIDs and Superregenerative Amplifiers 9 2.1 RFID Transponder Technology . . . . . . . . . . . . . . . . . . . . 9 2.1.1 Chipless RFID Transponders . . . . . . . . . . . . . . . . . 10 2.1.2 Semiconductor based RFID Transponders . . . . . . . . . . 11 2.1.2.1 Passive Transponders . . . . . . . . . . . . . . . . 11 2.1.2.2 Active Transponders . . . . . . . . . . . . . . . . . 13 2.2 RFID Interrogator Architectures . . . . . . . . . . . . . . . . . . . 18 2.2.1 Interferometer based Interrogator . . . . . . . . . . . . . . . 19 2.2.2 Ultra-wideband Interrogator . . . . . . . . . . . . . . . . . . 20 2.2.3 Continuous Wave Interrogators . . . . . . . . . . . . . . . . 21 2.3 Coupling Dependent Range and Operating Frequencies . . . . . . . 25 2.4 RFID Ranging Techniques . . . . . . . . . . . . . . . . . . . . . . . 28 2.4.0.1 Received Signal Strength based Ranging . . . . . 28 2.4.0.2 Phase based Ranging . . . . . . . . . . . . . . . . 30 2.4.0.3 Time based Ranging . . . . . . . . . . . . . . . . . 30 2.5 Architecture Selection for Proof of Concept Systems . . . . . . . . 32 2.6 Superregenerative Amplifier (SRA) . . . . . . . . . . . . . . . . . . 35 2.6.1 Fundamentals . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.6.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . 42 2.6.3 Frequency Domain Characteristics . . . . . . . . . . . . . . 45 2.7 Semiconductor Technologies for RFIC Design . . . . . . . . . . . . 48 2.7.1 Silicon Germanium BiCMOS . . . . . . . . . . . . . . . . . 48 2.7.2 Silicon-on-Insulator . . . . . . . . . . . . . . . . . . . . . . . 48 3 24GHz Superregenerative Transponder based Identification and Rang- ing System 51 3.1 System Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.1.1 SRT Identification and Ranging . . . . . . . . . . . . . . . . 51 3.1.2 Power Link Analysis . . . . . . . . . . . . . . . . . . . . . . 55 3.1.3 Non-idealities . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.1.4 SRA Quench Frequency Shift Keying for data transfer . . . 61 3.1.5 Knowledge Gained . . . . . . . . . . . . . . . . . . . . . . . 63 3.2 RFIC Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3.2.1 Low Power Direct Antenna Drive CMOS SRA IC . . . . . . 66 3.2.1.1 Circuit analysis and design . . . . . . . . . . . . . 66 3.2.1.2 Characterization . . . . . . . . . . . . . . . . . . . 69 3.2.2 Direct Antenna Drive SiGe SRA ICs . . . . . . . . . . . . . 71 3.2.2.1 Stacked Transistor Cross-coupled Quenchable Oscillator . . . . . . . . . . . . . . . . . . . . . . . . 72 3.2.2.1.1 Resonator . . . . . . . . . . . . . . . . . . 72 3.2.2.1.2 Output Network . . . . . . . . . . . . . . 75 3.2.2.1.3 Stacked Transistor Cross-coupled Pair and Loop Gain . . . . . . . . . . . . . . . . . 77 3.2.2.2 Quench Waveform Design . . . . . . . . . . . . . . 85 3.2.2.3 Characterization . . . . . . . . . . . . . . . . . . . 89 3.2.3 Antenna Diversity SiGe SRA IC with Integrated Quench Pulse Shaping . . . . . . . . . . . . . . . . . . . . . . . . . . 91 3.2.3.1 Circuit Analysis and Design . . . . . . . . . . . . 91 3.2.3.1.1 Crosscoupled Pair and Sampling Current 94 3.2.3.1.2 Common Base Input Stage . . . . . . . . 95 3.2.3.1.3 Cascode Output Stage . . . . . . . . . . . 96 3.2.3.1.4 Quench Pulse Shaping Circuit . . . . . . 96 3.2.3.1.5 Power Gain . . . . . . . . . . . . . . . . . 99 3.2.3.2 Characterization . . . . . . . . . . . . . . . . . . . 102 3.2.4 Knowledge Gained . . . . . . . . . . . . . . . . . . . . . . . 103 3.3 Proof of Principle System Implementation . . . . . . . . . . . . . . 106 3.3.1 Superregenerative Transponders . . . . . . . . . . . . . . . 106 3.3.1.1 Bandwidth Enhanced Microstrip Patch Antennas 108 3.3.2 FMCW Radar Interrogator . . . . . . . . . . . . . . . . . . 114 3.3.3 Chirp Z-transform Based Data Analysis . . . . . . . . . . . 116 4 60GHz Single Antenna RFID Interrogator based Identification System 121 4.1 System Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 4.2 RFIC Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 4.2.1 Quasi-circulator ICs . . . . . . . . . . . . . . . . . . . . . . 125 4.2.1.1 Transmission Lines based Quasi-Circulator IC . . 126 4.2.1.2 Lumped Elements WPD based Quasi-Circulator . 130 4.2.1.3 Characterization . . . . . . . . . . . . . . . . . . . 134 4.2.1.4 Knowledge Gained . . . . . . . . . . . . . . . . . . 135 4.2.2 Folded Switching Stage Downconversion Mixer IC . . . . . 138 4.2.2.1 FSSDM Circuit Design . . . . . . . . . . . . . . . 138 4.2.2.2 Cascode Transconductance Stage . . . . . . . . . . 138 4.2.2.3 Folded Switching Stage with LC DC Feed . . . . . 142 4.2.2.4 LO Balun . . . . . . . . . . . . . . . . . . . . . . . 145 4.2.2.5 Backgate Tunable IF Stage and Offset Correction 146 4.2.2.6 Voltage Conversion Gain . . . . . . . . . . . . . . 147 4.2.2.7 Characterization . . . . . . . . . . . . . . . . . . . 150 4.2.2.8 Knowledge Gained . . . . . . . . . . . . . . . . . . 151 4.3 Proof of Principle System Implementation . . . . . . . . . . . . . . 154 5 Experimental Tests 157 5.1 24GHz System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 5.1.1 Ranging Experiments . . . . . . . . . . . . . . . . . . . . . 157 5.1.2 Roll Invariance Experiments . . . . . . . . . . . . . . . . . . 158 5.1.3 Joint Ranging and Data Transfer Experiments . . . . . . . 158 5.2 60GHz System Detection Experiments . . . . . . . . . . . . . . . . 165 6 Summary and Future Work 167 Appendices 171 A Derivation of Parameters for CB Amplifier with Base Feedback Capac- itance 173 B Definitions 177 C 24GHz Experiment Setups 179 D 60 GHz Experiment Setups 183 References 185 List of Original Publications 203 List of Abbreviations 207 List of Symbols 213 List of Figures 215 List of Tables 223 Curriculum Vitae 22

Passive und aktive Radio Frequency Identification Tags im 60-GHz-Band

Die Einführung des millimeter-Wellen-Bandes eröffnet neue Perspektiven für die Radio Frequency Identification (RFID) Kommunikationssysteme. Der Enwurf des Systems im 60-GHz-Band ermöglicht die Implementierung der On-Chip Antenne und darüber hinaus die Implementierung eines RFID-Tags auf einem einzigen Chip. Dennoch ist es aufgrund der gesetzlichen Beschränkung der effektiven isotropen Strahlungsleistung (EIRP) des Lesegeräts und der erhöhten Freiraum-Dielektrikumsverluste eine Herausforderung, eine zuverlässige Kommunikationsreichweite von mehreren Millimetern zu erreichen. Neue Lösungen sind für jeden Block sowohl im Lesegerät als auch im Single-Chip-Tag erforderlich. Obwohl das Lesegerät batteriebetrieben ist, ist es immer noch eine Herausforderung, die maximal zulässigen 20 dBm IERP des Lesersenders energieeffizient zu erzeugen. Darüber hinaus sollte der Empfänger einen ausreichenden Dynamikbereich haben, um das vom Tag kommende Signal zu erkennen. Auf der Tag-Seite sind die Hauptherausforderungen das Co-Design der effizienten On-Chip-Antennen-Implementierung, die hochempfindliche Gleichrichter-Implementierung und das Rückkommunikationskonzept. Diese Arbeit konzentriert sich auf die Machbarkeitsstudie des Single-Chip-RFID-Tags und die Implementierung im Millimeterwellenbereich. Es werden zwei Rückkommunikationskonzepte untersucht - Backscattering-Rückkommunikation und eine Kommunikation unter Verwendung von Ultra-Low-Power (ULP) Radios. Beide werden in einem 22 nm FDSOI Prozess auf einem Substrat mit geringem Widerstand implementiert. Beide Tags arbeiten mit einer Versorgungsspannung von 0,4 V, um die Kommunikationsreichweite zu maximieren. Die Link-Budgets sind so ausgelegt, dass sie die regulatorischen Beschränkungen einhalten. Die Auswahl des Technologieknotens wird begründet. Verschiedene Aspekte im Zusammenhang mit der Technologie werden diskutiert, wie z. B. Geräteleistung, passiver Qualitätsfaktor, Leistungsdichte der Kondensatoren. Der Backscattering RFID-Tag wird zuerst entworfen, da er eine relativ einfachere Topologie hat. Die Probleme der Gleichrichterempfindlichkeit im Rahmen des analogen Frontends, der On-Chip-Antenneneffizienz und der konjugierten Anpassung beider werden untersucht. Eine Kommunikationsreichweite von 5 mm wird angestrebt und realisiert. Um die Kommunikationsreichweite weiter zu erhöhen, wird in der zweiten Phase ein Tag mit einer aktiven Rückkommunikation implementiert. Hier wird die Gleichrichterempfindlichkeit weiter verbessert. Es wird ein 0,4V ULP Radio entworfen, das sich die Antenne mit dem Gleichrichter über einen Single-Pole- Double-Through (SPDT) Schalter teilt. Ein Abstand von 2 cm erwies sich als realisierbar, wobei die gesetzlichen Bestimmungen eingehalten und der dynamische Bereich des Leseempfängers nicht überschritten wurde. Es wird die höchste normalisierte Kommunikationsreichweite pro Leser-EIRP erreicht. Weitere Verbesserungsmöglichkeiten werden diskutiert

A high speed serializer/deserializer design

A Serializer/Deserializer (SerDes) is a circuit that converts parallel data into a serial stream and vice versa. It helps solve clock/data skew problems, simplifies data transmission, lowers the power consumption and reduces the chip cost. The goal of this project was to solve the challenges in high speed SerDes design, which included the low jitter design, wide bandwidth design and low power design. A quarter-rate multiplexer/demultiplexer (MUX/DEMUX) was implemented. This quarter-rate structure decreases the required clock frequency from one half to one quarter of the data rate. It is shown that this significantly relaxes the design of the VCO at high speed and achieves lower power consumption. A novel multi-phase LC-ring oscillator was developed to supply a low noise clock to the SerDes. This proposed VCO combined an LC-tank with a ring structure to achieve both wide tuning range (11%) and low phase noise (-110dBc/Hz at 1MHz offset). With this structure, a data rate of 36 Gb/s was realized with a measured peak-to-peak jitter of 10ps using 0.18microm SiGe BiCMOS technology. The power consumption is 3.6W with 3.4V power supply voltage. At a 60 Gb/s data rate the simulated peak-to-peak jitter was 4.8ps using 65nm CMOS technology. The power consumption is 92mW with 2V power supply voltage. A time-to-digital (TDC) calibration circuit was designed to compensate for the phase mismatches among the multiple phases of the PLL clock using a three dimensional fully depleted silicon on insulator (3D FDSOI) CMOS process. The 3D process separated the analog PLL portion from the digital calibration portion into different tiers. This eliminated the noise coupling through the common substrate in the 2D process. Mismatches caused by the vertical tier-to-tier interconnections and the temperature influence in the 3D process were attenuated by the proposed calibration circuit. The design strategy and circuits developed from this dissertation provide significant benefit to both wired and wireless applications

Design of Ka-Band Low Noise Amplifier Using CMOS Technology

In this paper, design of a Low Noise Amplifier is undertaken for higher frequency bands, particularly Ka-band. The designed LNA can be used in satellite transponders for the mentioned frequency band. Generally LNAs are the first block in a transponder and are very sophisticated in trems of noise performance. A common-source topology along with source degeneration is used to achieve low noise figure and linearity with high gain. The use of CMOS technology provides new applications in designing this amplifier. It offers designs at lower cost, reduced power consumption and higher levels of integration. Proposed circuit achieves a maximum gain of 23dB with a relatively low noise figure of 2.9dB. This system can work in Deep-Space region as part of a satellite transponder

Negative resistance amplifier circuit using GaAsFET modelled single MESFET

Negative resistance devices have attracted much attention in the wireless communication industry because of their low cost, better performance, high speed, and reduced power requirements. Although negative resistance circuits are non-linear circuits, they are associated with distortion, which may either be amplitude-to-amplitude distortion or amplitude-to-phase distortion. In this paper, a unique way of realizing a negative resistance amplifier is proposed using a single metal-semiconductor field-effect transistor (MESFET). Intermodulation distortion test (IMD) is performed to evaluate the characteristic response of the negative resistance circuit amplifier to different bias voltages using the harmonic balance (HB) of the advanced designed software (ADS 2016). The results obtained are compared to those of a conventional distributed amplifier. The findings of this study showed that the negative resistance amplifier spreads over a wider frequency output with reduced power requirements while the conventional distributed amplifier has a direct current (DC) offset with output voltage of 32.34 dBm

Study and design of an impulse radio UWB synthesizer for 3.1-10.6 GHz band in 28 NM CMOS FD-SOI technology

Orientador: Prof. Ph.D. André Augusto MarianoCoorientador: Prof. Ph.D. Rémy VaucheDissertação (mestrado) - Universidade Federal do Paraná, Setor de Tecnologia, Programa de Pós-Graduação em Engenharia Elétrica. Defesa : Curitiba, 21/03/2022Inclui referências: p. 107-110Resumo: Este trabalho de dissertação de mestrado apresenta o estudo e desenvolvimento de sintetizador de pulsos de radio ultra banda larga para a banda 3,1-10,6 GHz em tecnologia 28 nm CMOS FD-SOI. A primeira utilização dessa banda de frequência foi autorizada pela comissão federal de comunicações dos Estados Unidos em 2002. Visando a explorar essa banda de frequência, o padrão IEEE 802.15.4 escolheu as comunicações baseadas em pulsos de radio em detrimento das comunicações tradicionais de banda estreita. Uma linha importante de pesquisa e o estudo e desenvolvimento de um transmissor ultra banda larga, capaz de endereçar múltiplas bandas e múltiplos padrões diferentes, que e consistido em um sintetizador de pulsos de radio devendo ter a capacidade de cobrir a banda 3,1-10,6 GHz. Para atingir tal objetivo, visa-se a implementação de uma arquitetura versátil baseada em um gerador de pulsos constituído principalmente por um oscilador controlado por tensão, e um circuito de formatação da envoltória do pulso, em que e possível fazer ajuste da duração e da frequência central dos pulsos, e compensar variações PVT (Processo, Tensão e Temperatura). O objetivo principal deste trabalho de dissertação de mestrado e estudo e desenvolvimento de um sintetizador de pulsos baseado nessa arquitetura em tecnologia 28 nm CMOS FD-SOI, de maneira que esse circuito seja capaz de cobrir toda banda 3.1-10.6 GHz e ao mesmo tempo cumprir os requerimentos espectrais estabelecidos pelos padrões IEEE 802.15.4 e IEEE 802.15.6. No projeto do circuito proposto, utilizou-se a técnica de síntese de pulso por transposição de frequência, constituído principalmente por um oscilador local comutado, permitindo a redução do consumo de energia, em que o sinal produzido pelo oscilador e modulado por um pulso em banda base. Em relação a metodologia do projeto, trata-se de um projeto totalmente personalizado, em que se utilizou as logicas CMOS e CML (Logica Diferencial), e se considerou capacitâncias parasitas estimadas no intuito de melhorar o dimensionamento dos transistores. A arquitetura do oscilador escolhida neste projeto foi o oscilador em anel, a qual permite de se obter uma banda de frequência suficientemente alta. Acerca da formatação do pulso, escolheu-se uma envoltória possível de se implementar com circuito digital reprogramável, visando a endereçar os diferentes canais do padrão IEEE 802.15.4 e IEEE 802.15.6. O sistema implementado, em nível de esquemático de transistor considerando capacitâncias parasitas estimadas, apresenta um desempenho satisfatório sobre a toda a banda de frequência de interesse, em que os pulsos gerados respeitam os gabaritos espectrais impostos pelos padrões IEEE, evidenciando a capacidade do circuito prosposto de ser multi-banda e cobrir toda a banda de frequência de interesse. Em relação ao consumo de potência, esse e influenciado pela duração do pulso e sua frequência central. Ademais, obteve-se um consumo de potencia estática 14 µW e um consumo de energia por pulso emitido máximo de 308 pJ, em que para esse caso, o pulso apresenta um energia transmitida de 11,7 pJ por pulso, assim apresentando uma eficiência de 3,8 %.Abstract: This dissertation work concerns the study and design of an impulse radio ultra-wide band synthesizer for 3.1-10.6 GHz frequency band in 28 nm CMOS FD-SOI technology. Indeed, this frequency band exploitation was initially authorized by the federal communications commission of United States in 2002. Targeting to exploit this frequency band, the IEEE 802.15.4 standard has chosen the communications based on impulse radio instead of the traditional narrowband communications. Besides, the impulse radio communications should respect communications standards, like the IEEE 802.15.4 for wireless personal networks, or IEEE 802.15.6 for wireless body networks. These IEEE standards define the generated pulse bandwidth and its central frequency. An important line of research is the study and design of a multi-standard or multi-band UWB transmitter, consisted by a pulse synthesizer that should be able to address all the standardized channels. To accomplish this, a proposed solution reposes on design of versatile architecture based on pulse generator and an envelope shaping circuit, where it is possible to tune the pulse duration and central frequency, and also to compensate PVT variations (Process, Voltage and Temperature). The dissertation work main goal is the study and design of a pulse synthesizer based on this architecture in 28 nm CMOS FD-SOI technology, such that the designed system is capable to cover all the 3.1-10.6 GHz and at same time to comply the spectral requirements established by IEEE 802.15.4 and 802.15.6 standards. In relation of the proposed circuit design, it is applied the pulse synthesis technique based on frequency transposition, that is mainly composed by a local oscillator that can be turned on and off, which allows to reduce the power consumption. The generated oscillation is modulated by a baseband pulse. Concerning the design methodology, it is a full-custom project, where CMOS and CML logics were used, and estimated parasitic capacitances were considered to achieve more reliable transistor sizing. The oscillator architecture chosen is based on ring oscillator, which allows to reach a frequency range sufficiently large. For the pulse shaping, it was chosen a envelope that is feasible to implement with fully digital circuit, targeting to address all IEEE 802.15.4 and IEEE 802.15.6 standard channels. The implemented system presents, in schematic levels considering parasitic capacitances, a satisfactory performance over all the 3.1-10.6 GHz band, where the generated pulses respect the spectral requirements imposed by the IEEE standards, therefore indicating that the proposed circuit is multi-band and able to cover all frequency band of interest. In terms of power consumption, it was achieved a power leakage of 14 µW and a maximal energy per pulse consumption of 308 pJ, where for this case, the pulse has an emitted energy of 11.7 pJ per pulse, therefore a efficiency of 3.8 %