Intrinsic distortion of a fully differential BD-modulated Class-D amplifier with analog feedback

This paper presents a mathematical analysis of a fully differential BD-modulated Class-D amplifier with analog feedback, i.e., one having a bridge-tied-load output configuration with negative feedback and ternary PWM signal. Notwithstanding the highly nonlinear nature of the amplifier's operation, an extremely accurate closed-form expression for the audible output signal is derived and verified based on computer simulations. This expression demonstrates that there exist larger high-order intrinsic distortions (e.g., 5th-order harmonic distortion and intermodulation distortion) for BD-modulation, compared to that for AD-modulation (binary PWM signal). Furthermore, the 3rd-order harmonic distortion has a roughly parabolic response as a function of the magnitude of the input signal and reaches its peak when the modulation index of the input signal is around 0.7. Overall, the BD-modulated Class-D amplifier has a larger intrinsic distortion for small input signal but a smaller intrinsic distortion for large input signal, compared to AD-modulated designs

Design and Analysis of a Dual Supply Class H Audio Amplifier

abstract: Efficiency of components is an ever increasing area of importance to portable applications, where a finite battery means finite operating time. Higher efficiency devices need to be designed that don't compromise on the performance that the consumer has come to expect. Class D amplifiers deliver on the goal of increased efficiency, but at the cost of distortion. Class AB amplifiers have low efficiency, but high linearity. By modulating the supply voltage of a Class AB amplifier to make a Class H amplifier, the efficiency can increase while still maintaining the Class AB level of linearity. A 92dB Power Supply Rejection Ratio (PSRR) Class AB amplifier and a Class H amplifier were designed in a 0.24um process for portable audio applications. Using a multiphase buck converter increased the efficiency of the Class H amplifier while still maintaining a fast response time to respond to audio frequencies. The Class H amplifier had an efficiency above the Class AB amplifier by 5-7% from 5-30mW of output power without affecting the total harmonic distortion (THD) at the design specifications. The Class H amplifier design met all design specifications and showed performance comparable to the designed Class AB amplifier across 1kHz-20kHz and 0.01mW-30mW. The Class H design was able to output 30mW into 16Ohms without any increase in THD. This design shows that Class H amplifiers merit more research into their potential for increasing efficiency of audio amplifiers and that even simple designs can give significant increases in efficiency without compromising linearity.Dissertation/ThesisM.S. Electrical Engineering 201

High-speed Time-interleaved Digital-to-Analog Converter (TI-DAC) for Self-Interference Cancellation Applications

Nowadays, the need for higher data-rate is constantly growing to enhance the quality of the daily communication services. The full-duplex (FD) communication is exemplary method doubling the data-rate compared to half-duplex one. However, part of the strong output signal of the transmitter interferes to the receiver-side because they share the same antenna with limited attenuation and, as a result, the receiver’s performance is corrupted. Hence, it is critical to remove the leakage signal from the receiver’s path by designing another block called self-interference cancellation (SIC). The main goal of this dissertation is to develop the SIC block embedded in the current-mode FD receivers. To this end, the regenerated cancellation current signal is fed to the inputs of the base-band filter and after the mixer of a (direct-conversion) current-mode FD receiver. Since the pattern of the transmitter (the digital signal generated by DSP) is known, a high-speed digital-to-Analog converter (DAC) with medium-resolution can perfectly suppress main part of the leakage on the receiver path. A capacitive DAC (CDAC) is chosen among the available solutions because it is compatible with advanced CMOS technology for high-speed application and the medium-resolution designs. Although the main application of the design is to perform the cancellation, it can also be employed as a stand-alone DAC in the Analog (I/Q) transmitter. The SIC circuitry includes a trans-impedance amplifier (TIA), two DACs, high-speed digital circuits, and built-in-self-test section (BIST). According to the available specification for full-duplex communication system, the resolution and working frequency of the CDAC are calculated (designed) equal to 10-bit (3 binary+ 2 binary + 5 thermometric) and 1GHz, respectively. In order to relax the design of the TIA (settling time of the DAC), the CDAC implements using 2-way time-interleaved (TI) manner (the effective SIC frequency equals 2GHz) without using any calibration technique. The CDAC is also developed with the split-capacitor technique to lower the negative effects of the conventional binary-weighted DAC. By adding one extra capacitor on the left-side of the split-capacitor, LSB-side, the value of the split-capacitor can be chosen as an integer value of the unit capacitor. As a result, it largely enhances the linearity of the CADC and cancellation performance. If the block works as a stand-alone DAC with non-TI mode, the digital input code representing a Sinus waveform with an amplitude 1dB less than full-scale and output frequency around 10.74MHz, chosen by coherent sampling rule, then the ENOB, SINAD, SFDR, and output signal are 9.4-bit, 58.2 dB, 68.4dBc, and -9dBV. The simulated value of the |DNL| (static linearity) is also less than 0.7. The similar simulation was done in the SIC mode while the capacitive-array woks in the TI mode and cancellation current is set to the full-scale. Hence, the amount of cancelling the SI signal at the output of the TIA, SNDR, SFDR, SNDRequ. equals 51.3dB, 15.1 dB, 24dBc, 66.4 dB. The designed SIC cannot work as a closed-loop design. The layout was optimally drawn in order to minimize non-linearity, the power-consumption of the decoders, and reduce the complexity of the DAC. By distributing the thermometric cells across the array and using symmetrical switching scheme, the DAC is less subjected to the linear and gradient effect of the oxide. Based on the post-layout simulation results, the deviation of the design after drawing the layout is studied. To compare the results of the schematic and post-layout designs, the exact conditions of simulation above (schematic simulations) are used. When the block works as a stand-alone CDAC, the ENOB, SINAD, SFDR are 8.5-bit, 52.6 dB, 61.3 dBc. The simulated value of the |DNL| (static linearity) is also limited to 1.3. Likewise, the SI signal at the output of the TIA, SNDR, SFDR, SNDRequ. are equal to 44dB, 11.7 dB, 19 dBc, 55.7 dB

Design and Implementation of Switching Voltage Integrated Circuits Based on Sliding Mode Control

The need for high performance circuits in systems with low-voltage and low-power requirements has exponentially increased during the few last years due to the sophistication and miniaturization of electronic components. Most of these circuits are required to have a very good efficiency behavior in order to extend the battery life of the device. This dissertation addresses two important topics concerning very high efficiency circuits with very high performance specifications. The first topic is the design and implementation of class D audio power amplifiers, keeping their inherent high efficiency characteristic while improving their linearity performance, reducing their quiescent power consumption, and minimizing the silicon area. The second topic is the design and implementation of switching voltage regulators and their controllers, to provide a low-cost, compact, high efficient and reliable power conversion for integrated circuits. The first part of this dissertation includes a short, although deep, analysis on class D amplifiers, their history, principles of operation, architectures, performance metrics, practical design considerations, and their present and future market distribution. Moreover, the harmonic distortion of open-loop class D amplifiers based on pulse-width modulation (PWM) is analyzed by applying the duty cycle variation technique for the most popular carrier waveforms giving an easy and practical analytic method to evaluate the class D amplifier distortion and determine its specifications for a given linearity requirement. Additionally, three class D amplifiers, with an architecture based on sliding mode control, are proposed, designed, fabricated and tested. The amplifiers make use of a hysteretic controller to avoid the need of complex overhead circuitry typically needed in other architectures to compensate non-idealities of practical implementations. The design of the amplifiers based on this technique is compact, small, reliable, and provides a performance comparable to the state-of-the-art class D amplifiers, but consumes only one tenth of quiescent power. This characteristic gives to the proposed amplifiers an advantage for applications with minimal power consumption and very high performance requirements. The second part of this dissertation presents the design, implementation, and testing of switching voltage regulators. It starts with a description and brief analysis on the power converters architectures. It outlines the advantages and drawbacks of the main topologies, discusses practical design considerations, and compares their current and future market distribution. Then, two different buck converters are proposed to overcome the most critical issue in switching voltage regulators: to provide a stable voltage supply for electronic devices, with good regulation voltage, high efficiency performance, and, most important, a minimum number of components. The first buck converter, which has been designed, fabricated and tested, is an integrated dual-output voltage regulator based on sliding mode control that provides a power efficiency comparable to the conventional solutions, but potentially saves silicon area and input filter components. The design is based on the idea of stacking traditional buck converters to provide multiple output voltages with the minimum number of switches. Finally, a fully integrated buck converter based on sliding mode control is proposed. The architecture integrates the external passive components to deliver a complete monolithic solution with minimal silicon area. The buck converter employs a poly-phase structure to minimize the output current ripple and a hysteretic controller to avoid the generation of an additional high frequency carrier waveform needed in conventional solutions. The simulated results are comparable to the state-of-the-art works even with no additional post-fabrication process to improve the converter performance

GaN-Based High Efficiency Transmitter for Multiple-Receiver Wireless Power Transfer

Wireless power transfer (WPT) has attracted great attention from industry and academia due to high charging flexibility. However, the efficiency of WPT is lower and the cost is higher than the wired power transfer approaches. Efforts including converter optimization, power delivery architecture improvement, and coils have been made to increase system efficiency.In this thesis, new power delivery architectures in the WPT of consumer electronics have been proposed to improve the overall system efficiency and increase the power density.First, a two-stage transmitter architecture is designed for a 100 W WPT system. After comparing with other topologies, the front-end ac-dc power factor correction (PFC) rectifier employs a totem-pole rectifier. A full bridge 6.78 MHz resonant inverter is designed for the subsequent stage. An impedance matching network provides constant transmitter coil current. The experimental results verify the high efficiency, high PF, and low total harmonic distortion (THD).Then, a single-stage transmitter is derived based on the verified two-stage structure. By integration of the PFC rectifier and full bridge inverter, two GaN FETs are saved and high efficiency is maintained. The integrated DCM operated PFC rectifier provides high PF and low THD. By adopting a control scheme, the transmitter coil current and power are regulated. A simple auxiliary circuit is employed to improve the light load efficiency. The experimental results verify the achievement of high efficiency.A closed-loop control scheme is implemented in the single-stage transmitter to supply multiple receivers simultaneously. With a controlled constant transmitter current, the system provides a smooth transition during dynamically load change. ZVS detection circuit is proposed to protect the transmitter from continuous hard switching operation. The control scheme is verified in the experiments.The multiple-reciever WPT system with the single-stage transmitter is investigated. The system operating range is discussed. The method of tracking optimum system efficiency is studied. The system control scheme and control procedure, targeting at providing a wide system operating range, robust operation and capability of tracking the optimized system efficiency, are proposed. Experiment results demonstrate the WPT system operation

Low Power DC-DC Converters and a Low Quiescent Power High PSRR Class-D Audio Amplifier

High-performance DC-DC voltage converters and high-efficient class-D audio amplifiers are required to extend battery life and reduce cost in portable electronics. This dissertation focuses on new system architectures and design techniques to reduce area and minimize quiescent power while achieving high performance. Experimental results from prototype circuits to verify theory are shown. Firstly, basics on low drop-out (LDO) voltage regulators are provided. Demand for system-on-chip solutions has increased the interest in LDO voltage regulators that do not require a bulky off-chip capacitor to achieve stability, also called capacitor- less LDO (CL-LDO) regulators. Several architectures have been proposed; however, comparing these reported architectures proves difficult, as each has a distinct process technology and specifications. This dissertation compares CL-LDOs in a unified manner. Five CL-LDO regulator topologies were designed, fabricated, and tested under common design conditions. Secondly, fundamentals on DC-DC buck converters are presented and area reduction techniques for the external output filter, power stage, and compensator are proposed. A fully integrated buck converter using standard CMOS technology is presented. The external output filter has been fully-integrated by increasing the switching frequency up to 45 MHz. Moreover, a monolithic single-input dual-output buck converter is proposed. This architecture implements only three switches instead of the four switches used in conventional solutions, thus potentially reducing area in the power stage through proper design of the power switches. Lastly, a monolithic PWM voltage mode buck converter with compact Type-III compensation is proposed. This compensation scheme employs a combination of Gm-RC and Active-RC techniques to reduce the area of the compensator, while maintaining low quiescent power consumption and fast transient response. The proposed compensator reduces area by more than 45% when compared to an equivalent conventional Type-III compensator. Finally, basics on class-D audio amplifiers are presented and a clock-free current controlled class-D audio amplifier using integral sliding mode control is proposed. The proposed amplifier achieves up to 82 dB of power supply rejection ratio and a total harmonic distortion plus noise as low as 0.02%. The IC prototype’s controller consumes 30% less power than those featured in recently published works

GaN vs. Si for Class D Audio Applications

The demands and applications of modern power electronics are quickly moving past the maximum performance capabilities of Silicon devices. As the processing of Wide Bandgap (WBG) materials matures and the commercial availability of WBG devices grows, circuit designers are exploring many applications to exploit the performance benefits over traditional Silicon devices. This work examines the under-explored application of GaN-based Class D audio by providing a side-by-side comparison of enhancement-mode GaN devices with currently available Silicon MOSFETs. It is suggested that GaN in Class D audio will allow for lower heat radiation, smaller circuit footprints, and longer battery life as compared to Si MOSFETs with a negligible trade-off for quality of sound

Contributions on spectral control for the asymmetrical full bridge multilevel inverter

Las topologías de circuitos inversores multinivel pueden trabajar a tensiones y potencias mayores que las alcanzadas por convertidores convencionales de dos niveles. Además, la conversión multinivel reduce la distorsión armónica de las variables de salida y en algunos casos, a pesar del aumento de elementos de conmutación, también reduce las pérdidas de conversión al incrementarse el número de niveles. La reducción de distorsión alcanzada por el número de niveles puede aprovecharse para reducir las pérdidas de conmutación disminuyendo la frecuencia de las señales portadoras. Para reducir aún más esta frecuencia sin degradar el espectro, nosotros controlamos las pendientes de las portadoras triangulares. Primero se han desarrollado dos modelos analíticos para predecir el espectro del voltage de salida, dependiendo de: el índice de modulación MA, la razón de distribución de voltaje K de las fuentes de alimentación , y las cuatro pendientes de las portadoras{r1, r2, r3, r4}. El primer modelo considera el Muestreo Natural y se basa en Series Dobles de Fourier (SDF) mientras que el segundo modelo, utiliza la Serie Sencilla de Fourier (SSF) introduciendo el concepto de Muestreo Pseudo-Natural, una aproximación digital de la modulación natural. Ambos modelos son programados en Matlab, verificados con Pspice y validados con un prototipo experimental que contiene un modulador digital implementado con DSP.La concordancia entre las modulaciones natural y pseudo-natural, asi como entre sus respectivos modelos, es aprovechada por un algorítmo genético (AG) donde la THD es la función costo a reducir. Después de varios ensayos y de sintonizar el AG, se genera una matriz que contiene conjuntos de portadoras optimizadas dentro un rango específico de las variables {MA,K} y es probada con un segundo prototipo en lazo cerrado. Un lazo lento digital modifica las portadoras creadas por un dsPIC en modulaciones PWM; estas son demoduladas y sus amplitudes corregidas por un lazo de acción anticipada. Estas portadoras se comparan con una referencia sinusoidal que a su vez es modificada por variables de estado, generando finalmente la modulación multinivel en lazo cerrado. Los resultados finales demuestran la fiabilidad de la reducción de armónicos usando la programación de las pendientes de las portadoras. Palabras claves: inversor multinivel, PWM, distorsión armónica, modelo espectral, pendiente de portadora, conjunto de portadoras, distribución de niveles, Serie Doble de Fourier, Serie Simple de Fourier, muestreo natural, muestreo regular, muestreo pseudo-natural , Algoritmos Genéticos.Multilevel inverter (MI) topologies can work at higher voltage and higher power than conventional two-level converters. In addition, multilevel conversion reduces the output variables harmonic distortion and, sometimes, in spite of the devices-count increment, the conversion losses can also decrease by increasing the number of levels. The harmonic distortion reduction achieved by increasing the number of levels, can be used to further reducing the switching losses by decreasing the inverter carrier frequencies. To reduce even more the switching frequency without degrading output spectrum, we control the triangular carrier waveforms slopes. First, to achieve this target, two analytical models have been created in order to predict the inverter output voltage spectrum, depending on diverse parameters: the amplitude modulation index MA, the voltage distribution K of the inverter input sources, and the four carrier slopes {r1, r2, r3, r4}. The first model considers Natural Sampling and is based on Double Fourier Series (DFS) whereas the second model based on Simple Fourier Series (SFS), introduces the concept of Pseudo-Natural Sampling, as a digital approximation of the natural modulation. Both models are programmed in Matlab, verified with Pspice simulations and validated with a first experimental prototype with a DSP digital modulator.The good agreement between natural and pseudo-natural modulations, as well as their respective DFS and SFS models, is exploited by a Genetic Algorithm (GA) application where THD is the cost function to minimize. After testing and properly tuning the GA, a framework matrix containing the optimized carriers set for a specific range of variables {MA,K} is generated and then, tested with a second, closed-loop prototype. A slow digital loop modifies the carrier slopes created by dsPIC microcontroller as PWM modulations, whose amplitude, once demodulated, are affected by a feed-forward loop. These carriers, compared with a sinusoidal reference, state-feedback modified, generate finally the closed-loop multilevel modulation. The final results demonstrates the feasibility of harmonic reduction by means of carrier slopes programming. Keywords: multilevel inverter, PWM, harmonic distortion, spectral modeling, carrier slope, carriers set, level distribution, Double Fourier Series, Simple Fourier Series, natural sampling, regular sampling, pseudo-natural sampling, Genetic Algorithms