A reconfigurable multicarrier demodulator architecture

An architecture based on parallel and pipline design approaches has been developed for the Frequency Division Multiple Access/Time Domain Multiplexed (FDMA/TDM) conversion system. The architecture has two main modules namely the transmultiplexer and the demodulator. The transmultiplexer has two pipelined modules. These are the shared multiplexed polyphase filter and the Fast Fourier Transform (FFT). The demodulator consists of carrier, clock, and data recovery modules which are interactive. Progress on the design of the MultiCarrier Demodulator (MCD) using commercially available chips and Application Specific Integrated Circuits (ASIC) and simulation studies using Viewlogic software will be presented at the conference

Modem for the land mobile satellite channel

This paper describes a modem which has been developed and implemented using a digital signal processor (DSP) for a land mobile satellite demonstration system. The requirements of this digital modem were determined by the characteristics of the land mobile satellite channel. This paper discusses the algorithms which implement the differentiated phase shift keying (DPSK) demodulator. An algorithm is included which estimates symbol timing independent of carrier phase without the use of a square-law nonlinearity

Розробка автоматизованих систем керування в середовищі CODESYS

Розглянуто застосування сучасних програмних середовищ розробки програмного забезпечення для програмованих логічних контролерів на прикладі CoDeSys. Application of modern software development environments software for programmable logic controllers on the example of CoDeSys

Experimental Demonstration of Real Time Receiver for FDMA PON

International audienceFDMA PON provides high aggregate capacity (20-40Gbps) without requiring the user modules to operate at such high data rate. In this paper, we present for the first time a real time implementation of a FDM receiver in FPGA 1Gbitps in transceiver modules for an ONU and OLT

Towards generic satellite payloads: software radio

Satellite payloads are becoming much more complex with the evolution towards multimedia applications. Moreover satellite lifetime increases while standard and services evolve faster, necessitating a hardware platform that can evolves for not developing new systems on each change. The same problem occurs in terrestrial systems like mobile networks and a foreseen solution is the software defined radio technology. In this paper we describe a way of introducing this concept at satellite level to offer to operators the required flexibility in the system. The digital functions enabling this technology, the hardware components implementing the functions and the reconfiguration processes are detailed. We show that elements of the software radio for satellites exist and that this concept is feasible

Realization of Programmable BPSK Demodulator-Bit Synchronizer using Multirate Processing

This paper presents the design and implementation of programmable BPSK demodulator and bit synchronizer. The demodulator is based on the Costas loop design whereas the bit synchronizer is based on Gardner timing error detector. The advantage of this design is that it offers programmability using multi-rate processing and does not rely on computation of filter coefficients, NCO angle input for each specific data rate and thus avoids computational complexities. The algorithm and its application were verified on Matlab-Simulink and was implemented on ALTERA platform. A 32 kHz BPSK demodulator–bit synchronizer pair catering for data rates from 1 kbps to 8 kbps was implemented.DOI:http://dx.doi.org/10.11591/ijece.v4i3.556

Optimization of a Feedforward Symbol Timing Estimator Using Two Samples per Symbol for Optical Coherent QPSK Systems

A feedforward symbol timing estimator using only two samples per symbol is proposed and optimized for optical coherent QPSK signal. Simulation results are presented and discussed.Department of Electrical EngineeringDepartment of Electronic and Information Engineerin

Optimization of a feedforward symbol timing estimator using two samples per symbol for optical coherent QPSK systems

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On a Hybrid Preamble/Soft-Output Demapper Approach for Time Synchronization for IEEE 802.15.6 Narrowband WBAN

In this paper, we present a maximum likelihood (ML) based time synchronization algorithm for Wireless Body Area Networks (WBAN). The proposed technique takes advantage of soft information retrieved from the soft demapper for the time delay estimation. This algorithm has a low complexity and is adapted to the frame structure specified by the IEEE 802.15.6 standard for the narrowband systems. Simulation results have shown good performance which approach the theoretical mean square error limit bound represented by the Cramer Rao Bound (CRB)