Analysis of Digitally Controlled Delay Loop-Nand Gate For Glitch Free Design

This paper presents a glitch free NAND based digitally controlled delay-lines for the avoidance of glitches. DCDL circuit uses control bits which can be generated using circuits called driving circuits. Different techniques of driving circuits are proposed to reduce the power consumption and the critical path delay. The proposed NAND based DCDLs have been designed in 90nm CMOS technology and it is adopted in the PLL application in order to reduce the power and delay time too. The analysis of present and proposed NAND based DCDL has been represented. Simulation result shows that the circuits designed with modified DCDL reduce both the power consumption and critical path delay. DOI: 10.17762/ijritcc2321-8169.15022

BOOTH RECODED WALLACE TREE MULTIPLIER USING NAND BASED DIGITALLY CONTROLLED DELAY LINES

ABSTRACT Digital controlled delay line (DCDL) is a digital circuit used to provide the desired delay for a circuit whose delay line is controlled by a digital control word. There are wide varieties of approaches available for constructing the DCDL. The previous approach deals about designing a DCDL with and without glitches. More over Glitches are the most considerable factor that limits the use of DCDL in many applications. The Glitches in a circuit can be analyzed by increasing delay control code in a circuit. By reducing the number of glitches a delay line also further reduced. . In this paper NAND based DCDL improved using Wallace tree multiplier, which used to give an accurate value, as well increase speed of operation. It aims at additional reduction of latency and area of the Wallace tree multiplier using the delay control units based on the DCDL unit. The simulation have been carried out using modelsim and xilinx tools

INJECTION-LOCKING TECHNIQUES FOR MULTI-CHANNEL ENERGY EFFICIENT TRANSMITTER

Ph.DDOCTOR OF PHILOSOPH

DESIGN AND IMPLEMENTATION OF AN ALL-COTS DIGITAL BACK-END FOR A PULSE-DOPPLER SYNTHETIC APERTURE RADAR

Radar imaging techniques employing synthetic aperture radar (SAR) are ubiquitous in applications such as defense, remote sensing, space exploration, terrain mapping, and many others. However, to obtain fine image resolution, radar systems must be capable of utilizing large signal bandwidths. By the sampling theorem, a large signal bandwidth equates to a high sampling frequency, resulting in more expensive and complex digital electronics required to digitize and process the waveform. Using linear frequency modulated (LFM) pulses and stretch processing techniques, systems such as frequency-modulated continuous-wave (FMCW) radars reduce the required sampling rate at the expense of longer pulses, higher transmit duty cycle, and decreased pulse repetition frequency. While these tradeoffs are often acceptable, in many situations they are not, and a pulse-Doppler radar system is required. These systems can utilize LFM pulses with nearly any desired pulse length and pulse repetition frequency to perform imaging, but they must have an analog-to-digital converter (ADC) and back-end processing capable of handling the full waveform bandwidth, leading to increased cost, size, or both. At the University of Oklahoma’s Advanced Radar Research Center, a pulse-Doppler radar system for use in a SAR application is designed and built using only commercially available components to decrease the size and cost of the radar, specifically the digital back-end. A minimum size and weight is targeted for this system because it is desired to eventually fly the radar and form images on a lightweight airborne platform, such as a quad- or octo-copter. The challenge with using commercial parts for a custom digital pulse-Doppler radar is that it is difficult to meet the strict timing requirements inherent to pulse-Doppler radar while simultaneously meeting the high-bandwidth requirements imposed by SAR. In this thesis, the design and implementation of the digital back-end for the custom SAR system is presented. The focus is placed on designing a control system and clock distribution scheme in the digital back-end to ensure pulse to pulse coherence while maintaining ideal LFM spectral quality. Additionally, a calibration method is devised to provide accurate range measurements each time the radar is turned on even if the latency between the digital transmitter and receiver changes. At the conclusion of this work, it is shown that the radar system is capable of performing accurate pulse-Doppler radar through the generation of range-Doppler maps from data captured by the radar. The results of these tests indicate that the system is suitable for eventual use in SAR imaging applications

Voltage-to-Time Converter for High-Speed Time-Based Analog-to-Digital Converters

In modern complementary metal oxide semiconductor (CMOS) technologies, the supply voltage scales faster than the threshold voltage (Vth) of the transistors in successive smaller nodes. Moreover, the intrinsic gain of the transistors diminishes as well. Consequently, these issues increase the difficulty of designing higher speed and larger resolution analog-to-digital converters (ADCs) employing voltage-domain ADC architectures. Nevertheless, smaller transistor dimensions in state-of-the-art CMOS technologies leads to reduced capacitance, resulting in lower gate delays. Therefore, it becomes beneficial to first convert an input voltage to a 'time signal' using a voltage-to-time converter (VTC), instead of directly converting it into a digital output. This 'time-signal' could then be converted to a digital output through a time-to-digital converter (TDC) for complete analog-to-digital conversion. However, the overall performance of such an ADC will still be limited to the performance level of the voltage-to-time conversion process. Hence, this thesis presents the design of a linear VTC for a high-speed time-based ADC in 28 nm CMOS process. The proposed VTC consists of a sample-and-hold (S/H) circuit, a ramp generator and a comparator to perform the conversion of the input signal from the voltage to the time domain. Larger linearity is attained by integrating a constant current (with high output impedance) over a capacitor, generating a linear ramp. The VTC operates at 256 MSPS consuming 1.3 mW from 1 V supply with a full-scale 1 V pk-pk differential input signal, while achieving a time-domain output signal with a spurious-free-dynamic-range (SFDR) of 77 dB and a signal-to-noise-and-distortion ratio (SNDR) of 56 dB at close to Nyquist frequency (f = 126.5 MHz). The proposed VTC attains an output range of 2.7 ns, which is the highest linear output range for a VTC at this speed, published to date

The Design of Low Power Ultra-Wideband Transceiver

Ph.DDOCTOR OF PHILOSOPH

Beamforming ultra-wideband transmitter

Master'sMASTER OF ENGINEERIN