A 2.2 μW analog front-end for multichannel neural recording

In this paper an analog front-end for the multi-channel implantable recording of neural signals is presented. It is comprised by a two-stage AC-coupled low-noise amplifier (LNA) and a one stage AC-coupled variable gain amplifier (VGA). The proposed architecture employs highly power-noise efficient current reuse fully differential OTAs in the LNA stage and a fully differential folded cascode for the VGA stage. Simulation results in AMS 0.18μm validate the proposed architecture under process corners variations with an estimated power consumption of 2.2μm and 3.1 μVrms in-band noise.Ministerio de Economía y Competitividad TEC2016- 80923-POffice of Naval Research (USA) N00014111031

An implantable mixed-signal CMOS die for battery-powered in vivo blowfly neural recordings

© 2018 A mixed-signal die containing two differential input amplifiers, a multiplexer and a 50 KSPS, 10-bit SAR ADC, has been designed and fabricated in a 0.35 μm CMOS process for in vivo neural recording from freely moving blowflies where power supplied voltage drops quickly due to the space/weight limited insufficient capacity of the battery. The designed neural amplifier has a 66 + dB gain, 0.13 Hz-5.3 KHz bandwidth and 0.39% THD. A 20% power supply voltage drop causes only a 3% change in amplifier gain and 0.9-bit resolution degrading for SAR ADC while the on-chip data modulation reduces the chip size, rendering the designed chip suitable for battery-powered applications. The fabricated die occupies 1.1 mm2 while consuming 238 μW, being suitable for implantable neural recordings from insects as small as a blowfly for electrophysiological studies of their sensorimotor control mechanisms. The functionality of the die has been validated by recording the signals from identified interneurons in the blowfly visual system

Recent Advances in Neural Recording Microsystems

The accelerating pace of research in neuroscience has created a considerable demand for neural interfacing microsystems capable of monitoring the activity of large groups of neurons. These emerging tools have revealed a tremendous potential for the advancement of knowledge in brain research and for the development of useful clinical applications. They can extract the relevant control signals directly from the brain enabling individuals with severe disabilities to communicate their intentions to other devices, like computers or various prostheses. Such microsystems are self-contained devices composed of a neural probe attached with an integrated circuit for extracting neural signals from multiple channels, and transferring the data outside the body. The greatest challenge facing development of such emerging devices into viable clinical systems involves addressing their small form factor and low-power consumption constraints, while providing superior resolution. In this paper, we survey the recent progress in the design and the implementation of multi-channel neural recording Microsystems, with particular emphasis on the design of recording and telemetry electronics. An overview of the numerous neural signal modalities is given and the existing microsystem topologies are covered. We present energy-efficient sensory circuits to retrieve weak signals from neural probes and we compare them. We cover data management and smart power scheduling approaches, and we review advances in low-power telemetry. Finally, we conclude by summarizing the remaining challenges and by highlighting the emerging trends in the field

Compressive Sensing and Multichannel Spike Detection for Neuro-Recording Systems

RÉSUMÉ Les interfaces cerveau-machines (ICM) sont de plus en plus importantes dans la recherche biomédicale et ses applications, tels que les tests et analyses médicaux en laboratoire, la cérébrologie et le traitement des dysfonctions neuromusculaires. Les ICM en général et les dispositifs d'enregistrement neuronaux, en particulier, dépendent fortement des méthodes de traitement de signaux utilisées pour fournir aux utilisateurs des renseignements sur l’état de diverses fonctions du cerveau. Les dispositifs d'enregistrement neuronaux courants intègrent de nombreux canaux parallèles produisant ainsi une énorme quantité de données. Celles-ci sont difficiles à transmettre, peuvent manquer une information précieuse des signaux enregistrés et limitent la capacité de traitement sur puce. Une amélioration de fonctions de traitement du signal est nécessaire pour s’assurer que les dispositifs d'enregistrements neuronaux peuvent faire face à l'augmentation rapide des exigences de taille de données et de précision requise de traitement. Cette thèse regroupe deux approches principales de traitement du signal - la compression et la réduction de données - pour les dispositifs d'enregistrement neuronaux. Tout d'abord, l’échantillonnage comprimé (AC) pour la compression du signal neuronal a été utilisé. Ceci implique l’usage d’une matrice de mesure déterministe basée sur un partitionnement selon le minimum de la distance Euclidienne ou celle de la distance de Manhattan (MDC). Nous avons comprimé les signaux neuronaux clairsemmés (Sparse) et non-clairsemmés et les avons reconstruit avec une marge d'erreur minimale en utilisant la matrice MDC construite plutôt. La réduction de données provenant de signaux neuronaux requiert la détection et le classement de potentiels d’actions (PA, ou spikes) lesquelles étaient réalisées en se servant de la méthode d’appariement de formes (templates) avec l'inférence bayésienne (Bayesian inference based template matching - BBTM). Par comparaison avec les méthodes fondées sur l'amplitude, sur le niveau d’énergie ou sur l’appariement de formes, la BBTM a une haute précision de détection, en particulier pour les signaux à faible rapport signal-bruit et peut séparer les potentiels d’actions reçus à partir des différents neurones et qui chevauchent. Ainsi, la BBTM peut automatiquement produire les appariements de formes nécessaires avec une complexité de calculs relativement faible.----------ABSTRACT Brain-Machine Interfaces (BMIs) are increasingly important in biomedical research and health care applications, such as medical laboratory tests and analyses, cerebrology, and complementary treatment of neuromuscular disorders. BMIs, and neural recording devices in particular, rely heavily on signal processing methods to provide users with nformation. Current neural recording devices integrate many parallel channels, which produce a huge amount of data that is difficult to transmit, cannot guarantee the quality of the recorded signals and may limit on-chip signal processing capabilities. An improved signal processing system is needed to ensure that neural recording devices can cope with rapidly increasing data size and accuracy requirements. This thesis focused on two signal processing approaches – signal compression and reduction – for neural recording devices. First, compressed sensing (CS) was employed for neural signal compression, using a minimum Euclidean or Manhattan distance cluster-based (MDC) deterministic sensing matrix. Sparse and non-sparse neural signals were substantially compressed and later reconstructed with minimal error using the built MDC matrix. Neural signal reduction required spike detection and sorting, which was conducted using a Bayesian inference-based template matching (BBTM) method. Compared with amplitude-based, energy-based, and some other template matching methods, BBTM has high detection accuracy, especially for low signal-to-noise ratio signals, and can separate overlapping spikes acquired from different neurons. In addition, BBTM can automatically generate the needed templates with relatively low system complexity. Finally, a digital online adaptive neural signal processing system, including spike detector and CS-based compressor, was designed. Both single and multi-channel solutions were implemented and evaluated. Compared with the signal processing systems in current use, the proposed signal processing system can efficiently compress a large number of sampled data and recover original signals with a small reconstruction error; also it has low power consumption and a small silicon area. The completed prototype shows considerable promise for application in a wide range of neural recording interfaces

Low-Noise Micro-Power Amplifiers for Biosignal Acquisition

There are many different types of biopotential signals, such as action potentials (APs), local field potentials (LFPs), electromyography (EMG), electrocardiogram (ECG), electroencephalogram (EEG), etc. Nerve action potentials play an important role for the analysis of human cognition, such as perception, memory, language, emotions, and motor control. EMGs provide vital information about the patients which allow clinicians to diagnose and treat many neuromuscular diseases, which could result in muscle paralysis, motor problems, etc. EEGs is critical in diagnosing epilepsy, sleep disorders, as well as brain tumors. Biopotential signals are very weak, which requires the biopotential amplifier to exhibit low input-referred noise. For example, EEGs have amplitudes from 1 μV [microvolt] to 100 μV [microvolt] with much of the energy in the sub-Hz [hertz] to 100 Hz [hertz] band. APs have amplitudes up to 500 μV [microvolt] with much of the energy in the 100 Hz [hertz] to 7 kHz [hertz] band. In wearable/implantable systems, the low-power operation of the biopotential amplifier is critical to avoid thermal damage to surrounding tissues, preserve long battery life, and enable wirelessly-delivered or harvested energy supply. For an ideal thermal-noise-limited amplifier, the amplifier power is inversely proportional to the input-referred noise of the amplifier. Therefore, there is a noise-power trade-off which must be well-balanced by the designers. In this work I propose novel amplifier topologies, which are able to significantly improve the noise-power efficiency by increasing the effective transconductance at a given current. In order to reject the DC offsets generated at the tissue-electrode interface, energy-efficient techniques are employed to create a low-frequency high-pass cutoff. The noise contribution of the high-pass cutoff circuitry is minimized by using power-efficient configurations, and optimizing the biasing and dimension of the devices. Sufficient common-mode rejection ratio (CMRR) and power supply rejection ratio (PSRR) are achieved to suppress common-mode interferences and power supply noises. Our design are fabricated in standard CMOS processes. The amplifiers’ performance are measured on the bench, and also demonstrated with biopotential recordings

Integrated Circuits and Systems for Smart Sensory Applications

Connected intelligent sensing reshapes our society by empowering people with increasing new ways of mutual interactions. As integration technologies keep their scaling roadmap, the horizon of sensory applications is rapidly widening, thanks to myriad light-weight low-power or, in same cases even self-powered, smart devices with high-connectivity capabilities. CMOS integrated circuits technology is the best candidate to supply the required smartness and to pioneer these emerging sensory systems. As a result, new challenges are arising around the design of these integrated circuits and systems for sensory applications in terms of low-power edge computing, power management strategies, low-range wireless communications, integration with sensing devices. In this Special Issue recent advances in application-specific integrated circuits (ASIC) and systems for smart sensory applications in the following five emerging topics: (I) dedicated short-range communications transceivers; (II) digital smart sensors, (III) implantable neural interfaces, (IV) Power Management Strategies in wireless sensor nodes and (V) neuromorphic hardware

Analog Front-End Circuits for Massive Parallel 3-D Neural Microsystems.

Understanding dynamics of the brain has tremendously improved due to the progress in neural recording techniques over the past five decades. The number of simultaneously recorded channels has actually doubled every 7 years, which implies that a recording system with a few thousand channels should be available in the next two decades. Nonetheless, a leap in the number of simultaneous channels has remained an unmet need due to many limitations, especially in the front-end recording integrated circuits (IC). This research has focused on increasing the number of simultaneously recorded channels and providing modular design approaches to improve the integration and expansion of 3-D recording microsystems. Three analog front-ends (AFE) have been developed using extremely low-power and small-area circuit techniques on both the circuit and system levels. The three prototypes have investigated some critical circuit challenges in power, area, interface, and modularity. The first AFE (16-channels) has optimized energy efficiency using techniques such as moderate inversion, minimized asynchronous interface for data acquisition, power-scalable sampling operation, and a wide configuration range of gain and bandwidth. Circuits in this part were designed in a 0.25μm CMOS process using a 0.9-V single supply and feature a power consumption of 4μW/channel and an energy-area efficiency of 7.51x10^15 in units of J^-1Vrms^-1mm^-2. The second AFE (128-channels) provides the next level of scaling using dc-coupled analog compression techniques to reject the electrode offset and reduce the implementation area further. Signal processing techniques were also explored to transfer some computational power outside the brain. Circuits in this part were designed in a 180nm CMOS process using a 0.5-V single supply and feature a power consumption of 2.5μW/channel, and energy-area efficiency of 30.2x10^15 J^-1Vrms^-1mm^-2. The last AFE (128-channels) shows another leap in neural recording using monolithic integration of recording circuits on the shanks of neural probes. Monolithic integration may be the most effective approach to allow simultaneous recording of more than 1,024 channels. The probe and circuits in this part were designed in a 150 nm SOI CMOS process using a 0.5-V single supply and feature a power consumption of only 1.4μW/channel and energy-area efficiency of 36.4x10^15 J^-1Vrms^-1mm^-2.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/98070/1/ashmouny_1.pd

Bidirectional Neural Interface Circuits with On-Chip Stimulation Artifact Reduction Schemes

Bidirectional neural interfaces are tools designed to “communicate” with the brain via recording and modulation of neuronal activity. The bidirectional interface systems have been adopted for many applications. Neuroscientists employ them to map neuronal circuits through precise stimulation and recording. Medical doctors deploy them as adaptable medical devices which control therapeutic stimulation parameters based on monitoring real-time neural activity. Brain-machine-interface (BMI) researchers use neural interfaces to bypass the nervous system and directly control neuroprosthetics or brain-computer-interface (BCI) spellers. In bidirectional interfaces, the implantable transducers as well as the corresponding electronic circuits and systems face several challenges. A high channel count, low power consumption, and reduced system size are desirable for potential chronic deployment and wider applicability. Moreover, a neural interface designed for robust closed-loop operation requires the mitigation of stimulation artifacts which corrupt the recorded signals. This dissertation introduces several techniques targeting low power consumption, small size, and reduction of stimulation artifacts. These techniques are implemented for extracellular electrophysiological recording and two stimulation modalities: direct current stimulation for closed-loop control of seizure detection/quench and optical stimulation for optogenetic studies. While the two modalities differ in their mechanisms, hardware implementation, and applications, they share many crucial system-level challenges. The first method aims at solving the critical issue of stimulation artifacts saturating the preamplifier in the recording front-end. To prevent saturation, a novel mixed-signal stimulation artifact cancellation circuit is devised to subtract the artifact before amplification and maintain the standard input range of a power-hungry preamplifier. Additional novel techniques have been also implemented to lower the noise and power consumption. A common average referencing (CAR) front-end circuit eliminates the cross-channel common mode noise by averaging and subtracting it in analog domain. A range-adapting SAR ADC saves additional power by eliminating unnecessary conversion cycles when the input signal is small. Measurements of an integrated circuit (IC) prototype demonstrate the attenuation of stimulation artifacts by up to 42 dB and cross-channel noise suppression by up to 39.8 dB. The power consumption per channel is maintained at 330 nW, while the area per channel is only 0.17 mm2. The second system implements a compact headstage for closed-loop optogenetic stimulation and electrophysiological recording. This design targets a miniaturized form factor, high channel count, and high-precision stimulation control suitable for rodent in-vivo optogenetic studies. Monolithically integrated optoelectrodes (which include 12 µLEDs for optical stimulation and 12 electrical recording sites) are combined with an off-the-shelf recording IC and a custom-designed high-precision LED driver. 32 recording and 12 stimulation channels can be individually accessed and controlled on a small headstage with dimensions of 2.16 x 2.38 x 0.35 cm and mass of 1.9 g. A third system prototype improves the optogenetic headstage prototype by furthering system integration and improving power efficiency facilitating wireless operation. The custom application-specific integrated circuit (ASIC) combines recording and stimulation channels with a power management unit, allowing the system to be powered by an ultra-light Li-ion battery. Additionally, the µLED drivers include a high-resolution arbitrary waveform generation mode for shaping of µLED current pulses to preemptively reduce artifacts. A prototype IC occupies 7.66 mm2, consumes 3.04 mW under typical operating conditions, and the optical pulse shaping scheme can attenuate stimulation artifacts by up to 3x with a Gaussian-rise pulse rise time under 1 ms.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/147674/1/mendrela_1.pd