Accelerated Successive Approximation Technique for Analog to Digital Converter Design

This thesis work presents a novel technique to reduce the number of conversion cycles for Successive Approximation register (SAR) Analog to Digital Converters (ADC), thereby potentially improving the conversion speed as well as reducing its power consumption. Conventional SAR ADCs employ the binary search algorithm and they update only one bound, either the upper or lower bound, of the search space during one conversion cycle. The proposed method, referred to as the Accelerated-SAR or A-SAR, is capable of updating both the lower and upper bounds in a single conversion cycle. Even in cases that it can update only one bound, it does more aggressively. The proposed technique is implemented in a 10-bit SAR ADC circuit with 0.5V power supply and rail-to-rail input range. To cope with the ultra-low voltage design challenge, Time-to-Digital conversion techniques are used in the implementation. Important design issues are also discussed for the charge scaling array and Voltage Controlled Delay Lines (VCDL), which are important building blocks in the ADC implementation

Energy-efficient data converter design in scaled CMOS technology

Data converters bridge the physical and digital worlds. They have been the crucial building blocks in modern electronic systems, and are expected to have a growing significance in the booming era of Internet-of-Things (IoT) and 5G communications. The applications raise energy-efficiency requirements for both low-speed and high-speed converters since they are widely deployed in wireless sensor nodes and portable devices. To explore the solutions, the author worked on three directions: 1) techniques to improve the efficiency of the low-speed converters including the comparator; 2) techniques to develop high-speed data converters including the reference stabilization; 3) new architecture to improve the efficiency of the capacitance-to-digital converter (CDC). In the first part, a power-efficient 10-bit SAR ADC featured with a gain-boosted dynamic comparator is presented. In energy-constrained applications, the converter is usually supplied with low supply voltage (e.g., 0.3 V-0.5 V), which reduces the comparator pre-amplifier (pre-amp) gain and results in higher noise. A novel comparator topology with a dynamic common-gate stage is proposed to increase the pre-amplification gain, thereby reducing noise and offset. Besides, statistical estimation and loading switching techniques are combined to further improve energy efficiency. A 40-nm CMOS prototype achieves a Walden FoM of 1.5 fJ/conversion-step while operating at 100-kS/s from a 0.5-V supply. To further improve the energy-efficiency of the comparator, a novel dynamic pre-amp is proposed. By using an inverter-based input pair powered by a floating reservoir capacitor, the pre-amp realizes both current reuse and dynamic bias, thereby significantly boosting g [subscript m] /I [subscript D] and reducing noise. Moreover, it greatly reduces the influence of the input common-mode (CM) voltage on the comparator performance, including noise, offset, and delay. A prototype comparator in 180-nm achieves 46-μV input-referred noise while consuming only 1 pJ per comparison under 1.2-V supply, which represents greater than 7 times energy efficiency boost compared to that of a Strong-Arm (SA) latch. The second part of this dissertation focuses on high-speed data converter techniques. A 10-bit high-speed two-stage loop-unrolled SAR ADC is presented. To reduce the SAR logic delay and power, each bit uses a dedicated comparator to store its output and generate an asynchronous clock for the next comparison. To suppress the comparator offset mismatch induced non-linearity, a shared pre-amp are employed in the second fine stage, which is implemented by a dynamic latch to avoid static power consumption. The prototype ADC in 40-nm CMOS achieves 55-dB peak SNDR at 200-MS/s sampling rate without any calibration. A key limiting factor for the SAR ADC to simultaneously achieve high speed and high resolution is the reference ripple settling problem caused by DAC switching. Unlike prior techniques that aim to minimize the reference ripple which requires large reference buffer power or on-chip decoupling capacitance area, this work proposes a new perspective: it provides an extra path for the full-sized reference ripple to couple to the comparator but with an opposite polarity, so that the effect of the reference ripple is canceled out, thus ensuring an accurate conversion result. The prototype 10-bit 120-MS/s SAR ADC is fabricated in 40-nm CMOS process and achieves an SNDR of 55 dB with only 3 pF reference decoupling capacitor. Finally, this dissertation also presents the design of an incremental time-domain two-step CDC. Unlike the classic two-step CDC, this work replaces the OTA-based active-RC integrator with a VCO-based integrator and performs time domain (TD) ΔΣ modulation. The VCO is mostly digital and consumes low power. Featuring the infinite DC gain in phase domain and intrinsic spatial phase quantization, this TDΔΣ enables a CDC design, achieving 85-dB SQNR by having only a 4-bit quantizer, a 1st-order loop and a low OSR of 15. The prototype fabricated in 40-nm CMOS achieves a resolution of 0.29 fF while dissipating only 0.083 nJ per conversion, which improves the energy efficiency by greater than 2 times comparing to that of state-of-the-art CDCsElectrical and Computer Engineerin

Resource-Constrained Acquisition Circuits for Next Generation Neural Interfaces

The development of neural interfaces allowing the acquisition of signals from the cortex of the brain has seen an increasing amount of interest both in academic research as well as in the commercial space due to their ability to aid people with various medical conditions, such as spinal cord injuries, as well as their potential to allow more seamless interactions between people and machines. While it has already been demonstrated that neural implants can allow tetraplegic patients to control robotic arms, thus to an extent returning some motoric function, the current state of the art often involves the use of heavy table-top instruments connected by wires passing through the patient’s skull, thus making the applications impractical and chronically infeasible. Those limitations are leading to the development of the next generation of neural interfaces that will overcome those issues by being minimal in size and completely wireless, thus paving a way to the possibility of their chronic application. Their development however faces several challenges in numerous aspects of engineering due to constraints presented by their minimal size, amount of power available as well as the materials that can be utilised. The aim of this work is to explore some of those challenges and investigate novel circuit techniques that would allow the implementation of acquisition analogue front-ends under the presented constraints. This is facilitated by first giving an overview of the problematic of recording electrodes and their electrical characterisation in terms of their impedance profile and added noise that can be used to guide the design of analogue front-ends. Continuous time (CT) acquisition is then investigated as a promising signal digitisation technique alternative to more conventional methods in terms of its suitability. This is complemented by a description of practical implementations of a CT analogue-to-digital converter (ADC) including a novel technique of clockless stochastic chopping aimed at the suppression of flicker noise that commonly affects the acquisition of low-frequency signals. A compact design is presented, implementing a 450 nW, 5.5 bit ENOB CT ADC, occupying an area of 0.0288 mm2 in a 0.18 μm CMOS technology, making this the smallest presented design in literature to the best of our knowledge. As completely wireless neural implants rely on power delivered through wireless links, their supply voltage is often subject to large high frequency variations as well voltage uncertainty making it necessary to design reference circuits and voltage regulators providing stable reference voltage and supply in the constrained space afforded to them. This results in numerous challenges that are explored and a design of a practical implementation of a reference circuit and voltage regulator is presented. Two designs in a 0.35 μm CMOS technology are presented, showing respectively a measured PSRR of ≈60 dB and ≈53 dB at DC and a worst-case PSRR of ≈42 dB and ≈33 dB with a less than 1% standard deviation in the output reference voltage of 1.2 V while consuming a power of ≈7 μW. Finally, ΣΔ modulators are investigated for their suitability in neural signal acquisition chains, their properties explained and a practical implementation of a ΣΔ DC-coupled neural acquisition circuit presented. This implements a 10-kHz, 40 dB SNDR ΣΔ analogue front-end implemented in a 0.18 μm CMOS technology occupying a compact area of 0.044 μm2 per channel while consuming 31.1 μW per channel.Open Acces

Analog Front-End Circuits for Massive Parallel 3-D Neural Microsystems.

Understanding dynamics of the brain has tremendously improved due to the progress in neural recording techniques over the past five decades. The number of simultaneously recorded channels has actually doubled every 7 years, which implies that a recording system with a few thousand channels should be available in the next two decades. Nonetheless, a leap in the number of simultaneous channels has remained an unmet need due to many limitations, especially in the front-end recording integrated circuits (IC). This research has focused on increasing the number of simultaneously recorded channels and providing modular design approaches to improve the integration and expansion of 3-D recording microsystems. Three analog front-ends (AFE) have been developed using extremely low-power and small-area circuit techniques on both the circuit and system levels. The three prototypes have investigated some critical circuit challenges in power, area, interface, and modularity. The first AFE (16-channels) has optimized energy efficiency using techniques such as moderate inversion, minimized asynchronous interface for data acquisition, power-scalable sampling operation, and a wide configuration range of gain and bandwidth. Circuits in this part were designed in a 0.25μm CMOS process using a 0.9-V single supply and feature a power consumption of 4μW/channel and an energy-area efficiency of 7.51x10^15 in units of J^-1Vrms^-1mm^-2. The second AFE (128-channels) provides the next level of scaling using dc-coupled analog compression techniques to reject the electrode offset and reduce the implementation area further. Signal processing techniques were also explored to transfer some computational power outside the brain. Circuits in this part were designed in a 180nm CMOS process using a 0.5-V single supply and feature a power consumption of 2.5μW/channel, and energy-area efficiency of 30.2x10^15 J^-1Vrms^-1mm^-2. The last AFE (128-channels) shows another leap in neural recording using monolithic integration of recording circuits on the shanks of neural probes. Monolithic integration may be the most effective approach to allow simultaneous recording of more than 1,024 channels. The probe and circuits in this part were designed in a 150 nm SOI CMOS process using a 0.5-V single supply and feature a power consumption of only 1.4μW/channel and energy-area efficiency of 36.4x10^15 J^-1Vrms^-1mm^-2.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/98070/1/ashmouny_1.pd

LOW POWER AND HIGH SIGNAL TO NOISE RATIO BIO-MEDICAL AFE DESIGN TECHNIQUES

The research work described in this thesis was focused on finding novel techniques to implement a low-power and noise Bio-Medical Analog Front End (BMEF) circuit technique to enable high-quality Electrocardiography (ECG) sensing. Usually, an ECG signal and several bio-medical signals are sensed from the human body through a pair of electrodes. The electrical characteristics of the very small amplitude (1u-10mV) signals are corrupted by random noise and have a significant dc offset. 50/60Hz power supply coupling noise is one of the biggest cross-talk signals compared to the thermally generated random noise. These signals are even AFE composed of an Instrumentation Amplifier (IA), which will have a better Common Mode rejection ratio (CMRR). The main function of the AFE is to convert the weak electrical Signal into large signals whose amplitude is large enough for an Analog Digital Converter (ADC) to detect without having any errors. A Variable Gain Amplifier (VGA) is sometimes required to adjust signal amplitude to maintain the dynamic range of the ADC. Also, the Bio-medical transceiver needs an accurate and temperature-independent reference voltage and current for the ADC, commonly known as Bandgap Reference Circuit (BGR). These circuits need to consume as low power as possible to enable these circuits to be powered from the battery. The work started with analysing the existing circuit techniques for the circuits mentioned above and finding the key important improvements required to reach the target specifications. Previously proposed IA is generated based on voltage mode signal processing. To improve the CMRR (119dB), we proposed a current mode-based IA with an embedded DC cancellation technique. State-of-the-art VGA circuits were built based on the degeneration principle of the differential pair, which will enable the variable gain purpose, but none of these techniques discussed linearity improvement, which is very important in modern CMOS technologies. This work enhances the total Harmonic distortion (THD) by 21dB in the worst case by exploiting the feedback techniques around the differential pair. Also, this work proposes a low power curvature compensated bandgap with 2ppm/0C temperature sensitivity while consuming 12.5uW power from a 1.2V dc power supply. All circuits were built in 45nm TSMC-CMOS technology and simulated with all the performance metrics with Cadence (spectre) simulator. The circuit layout was carried out to study post-layout parasitic effect sensitivity

Time and statistical information utilization in high efficiency sub-micron CMOS successive approximation analog to digital converters

In an industrial and consumer electronic marketplace that is increasingly demanding greater real-world interactivity in portable and distributed devices, analog to digital converter efficiency and performance is being carefully examined. The successive approximation (SAR) analog to digital converter (ADC) architecture has become popular for its high efficiency at mid-speed and resolution requirements. This is due to the one core single bit quantizer, lack of residue amplification, and large digital domain processing allowing for easy process scaling. This work examines the traditional binary capacitive SAR ADC time and statistical information and proposes new structures that optimize ADC performance. The Ternary SAR (TSAR) uses the quantizer delay information to enhance accuracy, speed and power consumption of the overall SAR while providing multi-level redundancy. The early reset merged capacitor switching SAR (EMCS) identifies lost information in the SAR subtraction and optimizes a full binary quanitzer structure for a Ternary MCS DAC. Residue Shaping is demonstrated in SAR and pipeline configurations to allow for an extra bit of signal to noise quantization ratio (SQNR) due to multi-level redundancy. The feedback initialized ternary SAR (FITSAR) is proposed which splits a TSAR into separate binary and ternary sub-ADC structures for speed and power benefits with an inter-stage encoding that not only maintains residue shaping across the binary SAR, but allows for nearly optimally minimal energy consumption for capacitive ternary DACs. Finally, the ternary SAR ideas are applied to R2R DACs to reduce power consumption. These ideas are tested both in simulation and with prototype results

Integrated Circuits and Systems for Smart Sensory Applications

Connected intelligent sensing reshapes our society by empowering people with increasing new ways of mutual interactions. As integration technologies keep their scaling roadmap, the horizon of sensory applications is rapidly widening, thanks to myriad light-weight low-power or, in same cases even self-powered, smart devices with high-connectivity capabilities. CMOS integrated circuits technology is the best candidate to supply the required smartness and to pioneer these emerging sensory systems. As a result, new challenges are arising around the design of these integrated circuits and systems for sensory applications in terms of low-power edge computing, power management strategies, low-range wireless communications, integration with sensing devices. In this Special Issue recent advances in application-specific integrated circuits (ASIC) and systems for smart sensory applications in the following five emerging topics: (I) dedicated short-range communications transceivers; (II) digital smart sensors, (III) implantable neural interfaces, (IV) Power Management Strategies in wireless sensor nodes and (V) neuromorphic hardware