The research work described in this thesis was focused on finding novel techniques to
implement a low-power and noise Bio-Medical Analog Front End (BMEF) circuit
technique to enable high-quality Electrocardiography (ECG) sensing. Usually, an ECG
signal and several bio-medical signals are sensed from the human body through a pair
of electrodes. The electrical characteristics of the very small amplitude (1u-10mV)
signals are corrupted by random noise and have a significant dc offset. 50/60Hz power
supply coupling noise is one of the biggest cross-talk signals compared to the thermally
generated random noise. These signals are even AFE composed of an Instrumentation
Amplifier (IA), which will have a better Common Mode rejection ratio (CMRR). The main
function of the AFE is to convert the weak electrical Signal into large signals whose
amplitude is large enough for an Analog Digital Converter (ADC) to detect without having
any errors. A Variable Gain Amplifier (VGA) is sometimes required to adjust signal
amplitude to maintain the dynamic range of the ADC. Also, the Bio-medical transceiver
needs an accurate and temperature-independent reference voltage and current for the
ADC, commonly known as Bandgap Reference Circuit (BGR). These circuits need to
consume as low power as possible to enable these circuits to be powered from the
battery.
The work started with analysing the existing circuit techniques for the circuits
mentioned above and finding the key important improvements required to reach the
target specifications. Previously proposed IA is generated based on voltage mode signal
processing. To improve the CMRR (119dB), we proposed a current mode-based IA with
an embedded DC cancellation technique. State-of-the-art VGA circuits were built based
on the degeneration principle of the differential pair, which will enable the variable gain
purpose, but none of these techniques discussed linearity improvement, which is very
important in modern CMOS technologies. This work enhances the total Harmonic
distortion (THD) by 21dB in the worst case by exploiting the feedback techniques around
the differential pair. Also, this work proposes a low power curvature compensated
bandgap with 2ppm/0C temperature sensitivity while consuming 12.5uW power from a
1.2V dc power supply. All circuits were built in 45nm TSMC-CMOS technology and
simulated with all the performance metrics with Cadence (spectre) simulator. The circuit
layout was carried out to study post-layout parasitic effect sensitivity
