Ultra Small Antenna and Low Power Receiver for Smart Dust Wireless Sensor Networks

Wireless Sensor Networks have the potential for profound impact on our daily lives. Smart Dust Wireless Sensor Networks (SDWSNs) are emerging members of the Wireless Sensor Network family with strict requirements on communication node sizes (1 cubic centimeter) and power consumption (< 2mW during short on-states). In addition, the large number of communication nodes needed in SDWSN require highly integrated solutions. This dissertation develops new design techniques for low-volume antennas and low-power receivers for SDWSN applications. In addition, it devises an antenna and low noise amplifier co-design methodology to increase the level of design integration, reduce receiver noise, and reduce the development cycle. This dissertation first establishes stringent principles for designing SDWSN electrically small antennas (ESAs). Based on these principles, a new ESA, the F-Inverted Compact Antenna (FICA), is designed at 916MHz. This FICA has a significant advantage in that it uses a small-size ground plane. The volume of this FICA (including the ground plane) is only 7% of other state-of-the-art ESAs, while its efficiency (48.53%) and gain (-1.38dBi) are comparable to antennas of much larger dimensions. A physics-based circuit model is developed for this FICA to assist system level design at the earliest stage, including optimization of the antenna performance. An antenna and low noise amplifier (LNA) co-design method is proposed and proven to be valid to design low power LNAs with the very low noise figure of only 1.5dB. To reduce receiver power consumption, this dissertation proposes a novel LNA active device and an input/ouput passive matching network optimization method. With this method, a power efficient high voltage gain cascode LNA was designed in a 0.13um CMOS process with only low quality factor inductors. This LNA has a 3.6dB noise figure, voltage gain of 24dB, input third intercept point (IIP3) of 3dBm, and power consumption of 1.5mW at 1.0V supply voltage. Its figure of merit, using the typical definition, is twice that of the best in the literature. A full low power receiver is developed with a sensitivity of -58dBm, chip area of 1.1mm2, and power consumption of 2.85mW

Design and Implementation of a Low‐Power Wireless Respiration Monitoring Sensor

Wireless devices for monitoring of respiration activities can play a major role in advancing modern home-based health care applications. Existing methods for respiration monitoring require special algorithms and high precision filters to eliminate noise and other motion artifacts. These necessitate additional power consuming circuitry for further signal conditioning. This dissertation is particularly focused on a novel approach of respiration monitoring based on a PVDF-based pyroelectric transducer. Low-power, low-noise, and fully integrated charge amplifiers are designed to serve as the front-end amplifier of the sensor to efficiently convert the charge generated by the transducer into a proportional voltage signal. To transmit the respiration data wirelessly, a lowpower transmitter design is crucial. This energy constraint motivates the exploration of the design of a duty-cycled transmitter, where the radio is designed to be turned off most of the time and turned on only for a short duration of time. Due to its inherent duty-cycled nature, impulse radio ultra-wideband (IR-UWB) transmitter is an ideal candidate for the implementation of a duty-cycled radio. To achieve better energy efficiency and longer battery lifetime a low-power low-complexity OOK (on-off keying) based impulse radio ultra-wideband (IR-UWB) transmitter is designed and implemented using standard CMOS process. Initial simulation and test results exhibit a promising advancement towards the development of an energy-efficient wireless sensor for monitoring of respiration activities

700mV low power low noise implantable neural recording system design

This dissertation presents the work for design and implementation of a low power, low noise neural recording system consisting of Bandpass Amplifier and Pipelined Analog to Digital Converter (ADC) for recording neural signal activities. A low power, low noise two stage neural amplifier for use in an intelligent Radio-Frequency Identification (RFID) based on folded cascode Operational Transconductance Amplifier (OTA) is utilized to amplify the neural signals. The optimization of the number of amplifier stages is discussed to achieve the minimum power and area consumption. The amplifier power supply is 0.7V. The midband gain of amplifier is 58.4dB with a 3dB bandwidth from 0.71 to 8.26 kHz. Measured input-referred noise and total power consumption are 20.7 μVrms and 1.90 μW respectively. The measured result shows that the optimizing the number of stages can achieve lower power consumption and demonstrates the neural amplifier's suitability for instu neutral activity recording. The advantage of power consumption of Pipelined ADC over Successive Approximation Register (SAR) ADC and Delta-Sigma ADC is discussed. An 8 bit fully differential (FD) Pipeline ADC for use in a smart RFID is presented in this dissertation. The Multiplying Digital to Analog Converter (MDAC) utilizes a novel offset cancellation technique robust to device leakage to reduce the input drift voltage. Simulation results of static and dynamic performance show this low power Pipeline ADC is suitable for multi-channel neural recording applications. The performance of all proposed building blocks is verified through test chips fabricated in IBM 180nm CMOS process. Both bench-top and real animal test results demonstrate the system's capability of recording neural signals for neural spike detection

A 16 channel high-voltage driver with 14 bit resolution for driving piezoelectric actuators

A high-voltage, 16 channel driver with a maximum voltage of 72 volt and 14 bit resolution in a high-voltage CMOS (HV-CMOS) process is presented. This design incorporates a 14 bit monotonic by design DAC together with a high-voltage complementary class AB output stage for each channel. All 16 channels are used for driving a piezoelectric actuator within the control loop of a micropositioning system. Since the output voltages are static most of the time, a class AB amplifier is used, implementing voltage feedback to achieve 14 bit accuracy. The output driver consists of a push-pull stage with a built-in output current limitation and high-impedance mode. Also a protection circuit is added which limits the internal current when the output voltage saturates against the high-voltage rail. The 14 bit resolution of each channel is generated with a segmented resistor string DAC which assures monotonic by design behavior by using leapfrogging of the buffers used between segments. A diagonal shuffle layout is used for the resistor strings leading to cancellation of first order process gradients. The dense integration of 16 channels with high peak currents results in crosstalk, countered in this design by using staggered switching and resampling of the output voltages

2.4 GHz wireless sensor network for smart electronic shirts

This paper presents a wireless sensor network for smart electronic shirts. This allows the monitoring of individual biomedical data, such the cardio-respiratory function. The solution chosen to transmit the body’s measured signals for further processing was the use of a wireless link, working at the 2.4 GHz ISM band. A radio frequency transceiver chip was designed in a UMC RF 0.18 µm CMOS process. The power supply of the transceiver is 1.8 V. Simulations show a power consumption of 12.9 mW. Innovative topics concerning efficient power management was taken into account during the design of the transceiver.(undefined

ANALYSIS AND DESIGN OF AN ULTRA-LOW POWER LOW-NOISE DTMOS BASED INSTRUMENTATION AMPLIFIER APPLIED TO THE PHYSIOLOGICAL SIGNAL ACQUISITION SYSTEM

With the rapid development of Internet of Things (IoT) technology and the popularity of portable devices, portable medical devices will become widely available soon. Physiological signal monitoring sensors are widely used for personal health management and long-term healthcare monitoring, especially for preventing acute illnesses and chronic disease monitoring for pediatric and elderly. Physiological signal monitoring sensors have the ability to monitor people's behavior in real-time for various daily activities, such as physiological signals that exhibit different waveforms and amplitudes when sleeping and awake. The real-time collected signals can be frequently compared to medical databases to detect abnormal health data for preventive healthcare. Therefore, an accurate and error-free system that provides high-quality monitoring of physiological signals is very important. Typically, an instrumentation amplifier (IA) is used for high accurate acquisition and amplification within this system. An IA with excellent performance gives patients safer health conditions and allows patients to have better health protection.This work introduces an ultra-low-power instrumentation amplifier operating at sub-0.4V voltage. Using dynamic threshold voltage MOSFET (DTMOS). The DTMOS reduces threshold voltage further and increases the driven current while the device is operating. Therefore, the DTMOS-based folded-cascode has been chosen, resulting in an increases the common-mode rejection ratio (CMRR) of the circuit while increasing the output signal swing compared over conventional topologies. The IA takes the benefit of the rail-to-rail common-mode feedback circuit and chopping to reduce flicker noise and DC offset. Reducing the chip area and power consumption leads to the output signal's high signal-to-noise ratio (SNR). The post-simulation shows that the circuit archives 45dB gain, DC to 2.07KHz operating bandwidth, and 0.8μW total power consumption. The simulated CMRR is 103dB, with 80dB power supply rejection ratio (PSRR). The simulated input reference noise is 140nV/√Hz (@100Hz) with 7.27 Noise Efficiency Factor (NEF).Keywords: Instrumentation Amplifier, DTMOS, rail-to-rail, chopping, clock boosting switch, physiological acquisition, bio-medical application

High frequency of low noise amplifier architecture for WiMAX application: A review

The low noise amplifier (LNA) circuit is exceptionally imperative as it promotes and initializes general execution performance and quality of the mobile communication system. LNA's design in radio frequency (R.F.) circuit requires the trade-off numerous imperative features' including gain, noise figure (N.F.), bandwidth, stability, sensitivity, power consumption, and complexity. Improvements to the LNA's overall performance should be made to fulfil the worldwide interoperability for microwave access (WiMAX) specifications' prerequisites. The development of front-end receiver, particularly the LNA, is genuinely pivotal for long-distance communications up to 50 km for a particular system with particular requirements. The LNA architecture has recently been designed to concentrate on a single transistor, cascode, or cascade constrained in gain, bandwidth, and noise figure

Mm-wave integrated wireless transceiver: enabling technology for high bandwidth short-range networking in cyber physical systems

Emerging application scenarios for Cyber Physical Systems often require the networking of sensing and actuation nodes at high data rate and through wireless links. Lot of surveillance and control systems adopt as input sensors distributed video cameras operating at different spectral ranges and covering different fields of view. Arrays of radio/light detection and ranging (Radar/Lidar) sensors are often used to detect the presence of targets, of their speeds, distance and direction. The relevant bandwidth requirement amounts to some Gbps. The wireless connection is essential for easy and flexible deployment of the sensing/actuation nodes. A key technology to keep low the size and weight of the nodes is the fully integration at mm-waves of wireless transceivers sustaining Gbps data rate. To this aim, this paper presents the design of 60&nbsp;GHz transceiver key blocks (Low Noise Amplifier, Power Amplifier, Antenna) to ensure connection distances up to 10&nbsp;m and data rate of several Gbps. Around 60&nbsp;GHz there are freely-available (unlicensed) worldwide several GHz of bandwidth. By using a CMOS Silicon-on-Insulator technology RF, analog and digital baseband circuitry can be integrated single-chip minimizing noise coupling. At mm-wave the wavelength is few mm and hence even the antenna is integrated on chip reducing cost and size vs. off-chip antenna solutions. The proposed transceiver enables at physical layer the implementation in compact nodes of links with data rates of several Gbps and up to 10&nbsp;m distance; this is suited for home/office scenarios, or on-board vehicles (cars, trains, ships, airplanes) or body area networks for healthcare and wellness

Design of an Ultra Low Power RFCMOS Transceiver for a Self-Powered IoT Node

In this thesis a transceiver characterized to consume ultra low power based in RFCMOS for a self-powered Internet of Things node is studied and designed. The transceiver consists in a simple Non-Coherent system, which means that the signal is picked up by the receiver based on energy detection, as a result it is one of the simplest existing transceivers once it does not need in the transmitter a complex pulse generator and certainly in the receiver as well. It is composed by an OOK modulator, a pulse generator that will determine the centre frequency and a driver amplifier connected to a 50W antenna for the transmitter. While in the receiver there is as first block a Low Noise Amplifier, a self-mixer that will prepare the signal for the integrator and a comparator working as a energy detector. The UWB transceiver will be able to operate with a centre frequency of 4.5 GHz and a bandwidth of at least 500 MHz. It is critical to notice that the system is consuming a value of 96 mW for the power and accomplishing the power spectrum density -43 dBm/MHz using an OOK modulation technique. The entire system was implemented with standard 130nm CMOS technology

Design of a Cost-Efficient Reconfigurable Pipeline ADC

Power budget is very critical in the design of battery-powered implantable biomedical instruments. High speed, high resolution and low power usually cannot be achieved at the same time. Therefore, a tradeoff must be made to compromise every aspect of those features. As the main component of the bioinstrument, high conversion rate, high resolution ADC consumes most of the power. Fortunately, based on the operation modes of the bioinstrument, a reconfigurable ADC can be used to solve this problem. The reconfigurable ADC will operate at 10-bit 40 MSPS for the diagnosis mode and at 8-bit 2.5 MSPS for the monitor mode. The ADC will be completely turned off if no active signal comes from sensors or if an off command is received from the antenna. By turning off the sample hold stage and the first two stages of the pipeline ADC, a significant power saving is achieved. However, the reconfigurable ADC suffers from two drawbacks. First, the leakage signals through the extra off-state switches in the third stage degrade the performance of the data converter. This situation tends to be even worse for high speed and high-resolution applications. An interference elimination technique has been proposed in this work to solve this problem. Simulation results show a significant attenuation of the spurious tones. Moreover, the transistors in the OTA tend to operate in weak inversion region due to the scaling of the bias current. The transistor in subthreshold is very slow due to the small transit frequency. In order to get a better tradeoff between the transconductance efficiency and the transit frequency, reconfigurable OTAs and scalable bias technique are devised to adjust the operating point from weak inversion to moderate inversion. The figure of merit of the reconfigurable ADC is comparable to the previously published conventional pipeline ADCs. For the 10-bit, 40 MSPS mode, the ADC attains a 56.9 dB SNDR for 35.4 mW power consumption. For the 8-bit 2.5 MSPS mode, the ADC attains a 49.2 dB SNDR for 7.9 mW power consumption. The area for the core layout is 1.9 mm2 for a 0.35 micrometer process