Investigation on EM radiations from interconnects in integrated circuits

Characterization and estimation of interconnections behavior in integrated circuits design before the implementation phase is of paramount importance. This behavior seen as microstrip antennas gets complex as the internal signal (square or sine waves) frequencies increase. Thus, they become the preferred path for the propagation of electromagnetic disturbances. In this work we have worked out the numerical modeling of the electromagnetic interactions characterizing the electromagnetic compatibility in the microstrip transmission lines. The effect of these electromagnetic interactions in different structures topologies are studied through the analysis of the influence of the supply signals frequency and structures. The spacing between transmission line tracks and the number of tracks superposition is modeled. The evolution and variation of the scheme parameters in the frequency domain are determined. The transmission lines are considered parallel of equal spacing and superposed tracks of equal spacing and thickness. The capacitance and inductance matrices are computed and discussed. The results are found to comply with current research outcomes

Kron Simulation of Field-to-line Coupling Using a Meshed and a Modified Taylor Cell

International audiencePrinted Circuit Board (PCB) traces play a role in the immunity of electronic products. Contrary to Integrated Circuits (ICs), the layout of PCB traces can be changed rather late in a product's design. Therefore, it is interesting to equip the PCB designer with simple tools that predict the immunity of his PCB traces. In this article, we compare two simulations of field-to-long line coupling based on Taylor's model. Firstly, the line is meshed into electrically short Taylor cells and numerically simulated using Kron's method. Secondly, we use one modified Taylor cell, which does not need meshing and is a closed-form, analytical result. The two simulations turn out to be equally precise on a straight microstrip line, the meshed simulation being more flexible, the simulation using a modified Taylor cell being faster

Polynomial-based surrogate modeling of RF and microwave circuits in frequency domain exploiting the multinomial theorem

A general formulation to develop EM-based polynomial surrogate models in frequency domain utilizing the multinomial theorem is presented in this paper. Our approach is especially suitable when the number of learning samples is very limited and no physics-based coarse model is available. We compare our methodology against other four surrogate modeling techniques: response surface modeling, support vector machines, generalized regression neural networks, and Kriging. Results confirm that our modeling approach has the best performance among these techniques when using a very small amount of learning base points on relatively small modeling regions. We illustrate our technique by developing a surrogate model for an SIW interconnect with transitions to microstrip lines, a dual band T-slot PIFA handset antenna, and a high-speed package interconnect. Examples are simulated on a commercially available 3D FEM simulator

Contribución al estudio de las interferencias electromagnéticas conducidas en circuitos integrados

This thesis is focused on the conducted electromagnetic Interference generated at Integrated Circuit (IC) Level. Recently, several electrical models have been proposed in order to describe EMI at IC level, but they have several limitations. The first drawback is that these electrical models do not take into account the wear-out mechanisms on the EMI behaviour. The wear-out mechanisms are due to the dielectric degradation when an electric stress is applied to the oxide gate. Due to this degradation, the MOSFET characteristics are shifted. Therefore, the evaluation of wear-out mechanisms allow the designers, during the IC design, to predict the circuit behaviour along its lifetime. However, the impact of these wear-out mechanisms on the conducted EMI drift at IC level has not been deeply investigated. Hence, one of the aims of this thesis will be focused on the impact of wear-out mechanisms in signal integrity and conducted EMI at IC level. Moreover, current integrated circuits have a high operation frequency. Thus, the electromagnetic noise induced on those devices presents a higher harmonic content. For this reason, the electronics industry requires electrical models to predict high frequency conducted emissions. In this sense, the other aim of this thesis will be focused on expanding the current EMI models beyond 1 GHz. The IC behaviour may be affected by temperature, as well as conducted emission levels. Therefore, the proposed electrical model will take into account the impact of temperature. The experimental results have been obtained with three integrated circuits, two of them are specific test chip designed by Freescale Semiconductor, Inc., and the third IC is a commercial circuit of Maxim Integrated Circuits. This document is structured in four chapters. Chapter 1 describes the main wear-out mechanisms and the electromagnetic compatibility at IC level. The different EMI produced at IC are explained. Also, it describes aging methods to characterize the impact of wear-out mechanisms on MOS devices. Furthermore, the EMI characterization methods are explained and different EMC electrical models are described. To confirm the accuracy of the EMC models, the ¿Feature Selective Validation¿ (FSV) technique has been used. On this chapter, the FSV method and its application on computational electromagnetism is detailed. The chapter ends with the state of the art on wear-out mechanisms and EMI at IC level. Chapter 2 analyzes the IC reliability. The IC aging of the MOSFET I-V curve characteristics is studied, for further EMI characterization of the impact of wear-out mechanisms. The experimental results are presented at the end of Chapter 2. Chapter 3 presents an electrical model to characterize the conducted emissions of an IC up to 3 GHz. This electrical model considers the impact of temperature. The proposed model is validated with experimental results and verified with the FSV method. Chapter 4 summarizes the conclusions of the thesis and the main contributions. In addition, a list of the publications derived from this thesis is included. Finally, the chapter presents the lines for future research.Esta tesis se centra en el estudio de las interferencias electromagnéticas (“Electromagnetic Interferences” o EMI) conducidas generadas a nivel de circuito integrado (CI). En la actualidad, existen modelos eléctricos para describir las EMI conducidas a nivel de CI, pero presentan ciertas limitaciones. La primera de ellas es que estos modelos no tienen en cuenta el impacto de los mecanismos de degradación sobre las EMI. Los mecanismos de degradación aparecen por el deterioro del dieléctrico debido al estrés eléctrico aplicado en el óxido de puerta. Estos mecanismos producen la variación de las características eléctricas de los dispositivos MOS. El estudio de estos efectos permite predecir, durante la etapa inicial del diseño, su impacto durante el tiempo de vida de los CI. Sin embargo, hasta la fecha, no se han llevado a cabo estudios del efecto de los mecanismos de degradación en las EMI conducidas a nivel de CI. Por lo tanto, uno de los primeros objetivos de la tesis será caracterizar el impacto de los mecanismos de degradación en la integridad de la señal y en las EMI conducidas a nivel de CI. Asimismo, los CI tienen una frecuencia de funcionamiento cada vez mayor, de modo que el ruido electromagnético generado por estos dispositivos tiene un contenido harmónico de más alta frecuencia. Es por esto que conviene tener modelos eléctricos que permitan modelizar las EMI de alta frecuencia. El segundo objetivo de la tesis consiste en modelizar las EMI conducidas más allá de la frecuencia de 1 GHz ya que los modelos actuales son válidos hasta esta frecuencia. La temperatura de funcionamiento del CI puede afectar al comportamiento del mismo, así como a los niveles de las emisiones conducidas. Por lo tanto será de interés que el modelo propuesto tenga en cuenta el impacto de la temperatura, ya que los modelos actuales únicamente son válidos para una temperatura de funcionamiento. La validación experimental se ha llevado a cabo sobre tres circuitos integrados, dos de ellos diseñados específicamente para este estudio por la empresa Freescale Semiconductor, Inc. y el tercer CI es un circuito comercial de Maxim Integrated Circuits. Este documento se compone de cuatro capítulos. El capítulo 1 empieza con la descripción de los principales mecanismos de degradación y de la compatibilidad electromagnética a nivel de circuito integrado. Se detallan las diferentes interferencias electromagnéticas que pueden producirse a nivel de circuito integrado. Se procede con la descripción de los métodos acelerados de envejecimiento para caracterizar el impacto de los mecanismos de degradación en los dispositivos MOS. Se continúa con una explicación de los métodos para caracterizar las EMI y la presentación de diferentes modelos EMC para su modelización. Para la validación de los estos modelos EMC se hace uso del método “Feature Selective Validation” (FSV). En este capítulo se da explicación al método FSV y su aplicación en el electromagnetismo computacional. Para finalizar el capítulo, se describe el estado actual de la investigación en el campo de los mecanismos de degradación y de las EMI a nivel de CI. En el capítulo 2 se analiza la fiabilidad de los CI. Se estudia el impacto de los mecanismos de degradación en el comportamiento de los transistores, para posteriormente estudiar el impacto de estos mecanismos en las EMI. El capítulo 2 se complementa con los resultados experimentales obtenidos en el laboratorio. El capítulo 3 se centra en la caracterización y el modelado de las EMI en los circuitos integrados. Se propone un modelo eléctrico para caracterizar las interferencias electromagnéticas conducidas hasta los 3 GHz y el impacto de la temperatura en las emisiones conducidas. El modelo propuesto es comprobado con medidas experimentales y verificado con el método FSV. Por último, el capítulo 4 resume las conclusiones de la tesis y las principales contribuciones. Además, en este capítulo se presenta las líneas de investigación futuras. Esta tesis se ha desarrollado dentro de una de las líneas de investigación del Grupo de Electrónica Industrial de Terrassa (“Terrassa Industrial Electronics Group” - TIEG), dentro del marco del proyecto de investigación TEC2009-09994, TEC2010-18550 y AGAUR 2009 SGR 142