DESTINY: A Comprehensive Tool with 3D and Multi-Level Cell Memory Modeling Capability

To enable the design of large capacity memory structures, novel memory technologies such as non-volatile memory (NVM) and novel fabrication approaches, e.g., 3D stacking and multi-level cell (MLC) design have been explored. The existing modeling tools, however, cover only a few memory technologies, technology nodes and fabrication approaches. We present DESTINY, a tool for modeling 2D/3D memories designed using SRAM, resistive RAM (ReRAM), spin transfer torque RAM (STT-RAM), phase change RAM (PCM) and embedded DRAM (eDRAM) and 2D memories designed using spin orbit torque RAM (SOT-RAM), domain wall memory (DWM) and Flash memory. In addition to single-level cell (SLC) designs for all of these memories, DESTINY also supports modeling MLC designs for NVMs. We have extensively validated DESTINY against commercial and research prototypes of these memories. DESTINY is very useful for performing design-space exploration across several dimensions, such as optimizing for a target (e.g., latency, area or energy-delay product) for a given memory technology, choosing the suitable memory technology or fabrication method (i.e., 2D v/s 3D) for a given optimization target, etc. We believe that DESTINY will boost studies of next-generation memory architectures used in systems ranging from mobile devices to extreme-scale supercomputers. The latest source-code of DESTINY is available from the following git repository: https://bitbucket.org/sparsh_mittal/destiny_v2

An Overview of DRAM-Based Security Primitives

Recent developments have increased the demand for adequate security solutions, based on primitives that cannot be easily manipulated or altered, such as hardware-based primitives. Security primitives based on Dynamic Random Access Memory (DRAM) can provide cost-efficient and practical security solutions, especially for resource-constrained devices, such as hardware used in the Internet of Things (IoT), as DRAMs are an intrinsic part of most contemporary computer systems. In this work, we present a comprehensive overview of the literature regarding DRAM-based security primitives and an extended classification of it, based on a number of different criteria. In particular, first, we demonstrate the way in which DRAMs work and present the characteristics being exploited for the implementation of security primitives. Then, we introduce the primitives that can be implemented using DRAM, namely Physical Unclonable Functions (PUFs) and True Random Number Generators (TRNGs), and present the applications of each of the two types of DRAM-based security primitives. We additionally proceed to assess the security such primitives can provide, by discussing potential attacks and defences, as well as the proposed security metrics. Subsequently, we also compare these primitives to other hardware-based security primitives, noting their advantages and shortcomings, and proceed to demonstrate their potential for commercial adoption. Finally, we analyse our classification methodology, by reviewing the criteria employed in our classification and examining their significance

Design and Development of Smart Brain-Machine-Brain Interface (SBMIBI) for Deep Brain Stimulation and Other Biomedical Applications

Machine collaboration with the biological body/brain by sending electrical information back and forth is one of the leading research areas in neuro-engineering during the twenty-first century. Hence, Brain-Machine-Brain Interface (BMBI) is a powerful tool for achieving such machine-brain/body collaboration. BMBI generally is a smart device (usually invasive) that can record, store, and analyze neural activities, and generate corresponding responses in the form of electrical pulses to stimulate specific brain regions. The Smart Brain-Machine-Brain-Interface (SBMBI) is a step forward with compared to the traditional BMBI by including smart functions, such as in-electrode local computing capabilities, and availability of cloud connectivity in the system to take the advantage of powerful cloud computation in decision making. In this dissertation work, we designed and developed an innovative form of Smart Brain-Machine-Brain Interface (SBMBI) and studied its feasibility in different biomedical applications. With respect to power management, the SBMBI is a semi-passive platform. The communication module is fully passive—powered by RF harvested energy; whereas, the signal processing core is battery-assisted. The efficiency of the implemented RF energy harvester was measured to be 0.005%. One of potential applications of SBMBI is to configure a Smart Deep-Brain-Stimulator (SDBS) based on the general SBMBI platform. The SDBS consists of brain-implantable smart electrodes and a wireless-connected external controller. The SDBS electrodes operate as completely autonomous electronic implants that are capable of sensing and recording neural activities in real time, performing local processing, and generating arbitrary waveforms for neuro-stimulation. A bidirectional, secure, fully-passive wireless communication backbone was designed and integrated into this smart electrode to maintain contact between the smart electrodes and the controller. The standard EPC-Global protocol has been modified and adopted as the communication protocol in this design. The proposed SDBS, by using a SBMBI platform, was demonstrated and tested through a hardware prototype. Additionally the SBMBI was employed to develop a low-power wireless ECG data acquisition device. This device captures cardiac pulses through a non-invasive magnetic resonance electrode, processes the signal and sends it to the backend computer through the SBMBI interface. Analysis was performed to verify the integrity of received ECG data

Wearable, Integrated EEG-fNIRS Technologies: A Review.

There has been considerable interest in applying electroencephalography (EEG) and functional near-infrared spectroscopy (fNIRS) simultaneously for multimodal assessment of brain function. EEG-fNIRS can provide a comprehensive picture of brain electrical and hemodynamic function and has been applied across various fields of brain science. The development of wearable, mechanically and electrically integrated EEG-fNIRS technology is a critical next step in the evolution of this field. A suitable system design could significantly increase the data/image quality, the wearability, patient/subject comfort, and capability for long-term monitoring. Here, we present a concise, yet comprehensive, review of the progress that has been made toward achieving a wearable, integrated EEG-fNIRS system. Significant marks of progress include the development of both discrete component-based and microchip-based EEG-fNIRS technologies; modular systems; miniaturized, lightweight form factors; wireless capabilities; and shared analogue-to-digital converter (ADC) architecture between fNIRS and EEG data acquisitions. In describing the attributes, advantages, and disadvantages of current technologies, this review aims to provide a roadmap toward the next generation of wearable, integrated EEG-fNIRS systems

Toward EEG-Assisted Hearing Aids: Objective Threshold Estimation Based on Ear-EEG in Subjects With Sensorineural Hearing Loss

Electrophysiological feedback on activity in the auditory pathway may potentially advance the next generation of hearing aids. Conventional electroencephalographic (EEG) systems are, however, impractical during daily life and incompatible with hearing aids. Ear-EEG is a method in which the EEG is recorded from electrodes embedded in a hearing aid like earpiece. The method therefore provides an unobtrusive way of measuring neural activity suitable for use in everyday life. This study aimed to determine whether ear-EEG could be used to estimate hearing thresholds in subjects with sensorineural hearing loss. Specifically, ear-EEG was used to determine physiological thresholds at 0.5, 1, 2, and 4 kHz using auditory steady-state response measurements. To evaluate ear-EEG in relation to current methods, thresholds were estimated from a concurrently recorded conventional scalp EEG. The threshold detection rate for ear-EEG was 20% lower than the detection rate for scalp EEG. Thresholds estimated using in-ear referenced ear-EEG were found to be elevated at an average of 5.9, 2.3, 5.6, and 1.5 dB relative to scalp thresholds at 0.5, 1, 2, and 4 kHz, respectively. No differences were found in the variance of means between in-ear ear-EEG and scalp EEG. In-ear ear-EEG, auditory steady-state response thresholds were found at 12.1 to 14.4 dB sensation level with an intersubject variation comparable to that of behavioral thresholds. Collectively, it is concluded that although further refinement of the method is needed to optimize the threshold detection rate, ear-EEG is a feasible method for hearing threshold level estimation in subjects with sensorineural hearing impairment.Funding Agencies|Oticon Foundation [15-0547]</p

Interface Circuits for Microsensor Integrated Systems

ca. 200 words; this text will present the book in all promotional forms (e.g. flyers). Please describe the book in straightforward and consumer-friendly terms. [Recent advances in sensing technologies, especially those for Microsensor Integrated Systems, have led to several new commercial applications. Among these, low voltage and low power circuit architectures have gained growing attention, being suitable for portable long battery life devices. The aim is to improve the performances of actual interface circuits and systems, both in terms of voltage mode and current mode, in order to overcome the potential problems due to technology scaling and different technology integrations. Related problems, especially those concerning parasitics, lead to a severe interface design attention, especially concerning the analog front-end and novel and smart architecture must be explored and tested, both at simulation and prototype level. Moreover, the growing demand for autonomous systems gets even harder the interface design due to the need of energy-aware cost-effective circuit interfaces integrating, where possible, energy harvesting solutions. The objective of this Special Issue is to explore the potential solutions to overcome actual limitations in sensor interface circuits and systems, especially those for low voltage and low power Microsensor Integrated Systems. The present Special Issue aims to present and highlight the advances and the latest novel and emergent results on this topic, showing best practices, implementations and applications. The Guest Editors invite to submit original research contributions dealing with sensor interfacing related to this specific topic. Additionally, application oriented and review papers are encouraged.

On-demand sensor node wake-up using solar panels and visible light communication

To significantly reduce, or eliminate completely, the energy waste caused by the standby (idle) mode of wireless sensor nodes, we propose a novel on-demand wake-up system, which allows the nodes to be put into sleep mode unless their activation is truly necessary. Although there have been many studies proposing RF-based wake-up radio systems, in this work, we develop the first visible light communication (VLC)-based wake-up system. The developed system can extend the existing VLC systems and can be exploited to derive new application areas such as VLC tags. The system uses an off-the-shell indoor solar panel as receptor device of the wake-up signal as well as for energy harvesting purposes, through which it is able to harvest enough energy for its autonomous work. The design, implementation details and the experimental evaluation results are presented, which include flickering characterization and wake-up range evaluations. The results show that the developed system achieve reasonable wake-up distances for indoor environments, mainly where the use of VLC systems are considered.Peer ReviewedPostprint (published version

Integrated Circuits and Systems for Smart Sensory Applications

Connected intelligent sensing reshapes our society by empowering people with increasing new ways of mutual interactions. As integration technologies keep their scaling roadmap, the horizon of sensory applications is rapidly widening, thanks to myriad light-weight low-power or, in same cases even self-powered, smart devices with high-connectivity capabilities. CMOS integrated circuits technology is the best candidate to supply the required smartness and to pioneer these emerging sensory systems. As a result, new challenges are arising around the design of these integrated circuits and systems for sensory applications in terms of low-power edge computing, power management strategies, low-range wireless communications, integration with sensing devices. In this Special Issue recent advances in application-specific integrated circuits (ASIC) and systems for smart sensory applications in the following five emerging topics: (I) dedicated short-range communications transceivers; (II) digital smart sensors, (III) implantable neural interfaces, (IV) Power Management Strategies in wireless sensor nodes and (V) neuromorphic hardware

Advances in closed-loop deep brain stimulation devices

BACKGROUND: Millions of patients around the world are affected by neurological and psychiatric disorders. Deep brain stimulation (DBS) is a device-based therapy that could have fewer side-effects and higher efficiencies in drug-resistant patients compared to other therapeutic options such as pharmacological approaches. Thus far, several efforts have been made to incorporate a feedback loop into DBS devices to make them operate in a closed-loop manner. METHODS: This paper presents a comprehensive investigation into the existing research-based and commercial closed-loop DBS devices. It describes a brief history of closed-loop DBS techniques, biomarkers and algorithms used for closing the feedback loop, components of the current research-based and commercial closed-loop DBS devices, and advancements and challenges in this field of research. This review also includes a comparison of the closed-loop DBS devices and provides the future directions of this area of research. RESULTS: Although we are in the early stages of the closed-loop DBS approach, there have been fruitful efforts in design and development of closed-loop DBS devices. To date, only one commercial closed-loop DBS device has been manufactured. However, this system does not have an intelligent and patient dependent control algorithm. A closed-loop DBS device requires a control algorithm to learn and optimize the stimulation parameters according to the brain clinical state. CONCLUSIONS: The promising clinical effects of open-loop DBS have been demonstrated, indicating DBS as a pioneer technology and treatment option to serve neurological patients. However, like other commercial devices, DBS needs to be automated and modernized