Nagy megbízhatóságú integrált mikro- és nanorendszerek új tesztelési és vizsgálati módszerei, különös tekintettel az ambient intelligence kihívásaira = New design verification and examination principles and methods for high reliability integrated micro-nano-systems with special attention to the challenges of ambient intelligence

A kutatás eredményeit mintegy 15 új publikációban fejtettük ki részletesen. Az elért eredményekben a következőkben foglalhatók össze: - Kutató és fejlesztő munkát végeztünk energiaforrással egybeintegrált érzékelők fejlesztése területén. - Kutató és fejlesztő munkákat végeztünk MEMS struktúrákba építhető tesztelő és öntesztelő struktúrák kifejlesztésére. Ezt a munkát a PATENT kiválósági hálózat nemzetközi projekt keretében különböző ad-hoc konzorciumokatban nemzetközi kooperációban végeztük. - Jelentős lépést értünk el a MEMS tokozások megbízhatósági vizsgálatában a termikus tranziens mérési módszer alkalmazásával. A kifejlesztett módszer több nemzetközi publikációban mutattuk be és a munka eredményeiből PhD disszertáció is készült. - Igen jelentős eredményeket értünk el a termikus anyagparaméterek pontosabb meghatározása területén. A témával foglalkozó publikációnkat az IEEE CPMT Best Paper díj adományozásával értékelte. - Jelentős eredményeket értünk el a mikrocsatornás hűtőszerkezetek hűtési tulajdonságainak minősítése területén. Az elért eredményeket 5 különböző nemzetközi kooperációban készült cikkben mutattuk be. | The research results are presented in detail in about 15 new publications. The achieved results can be summarized as follows: - Research and development work was accomplished in order to realize energy sources and sensors on the same chip. - Research and development work was carried out in order to develop new test and self test structures for the characterizations of MEMS systems. This work was done in the Framework of the PATENT Network of Excellence in different ad-hoc consortia. - Significant results were achieved in the field of reliability testing methods of MEMS packaging and MEMS etching with the help of the application of thermal transient testing. The newly developed methodology was presented in several international publications and it forms the basis of one PhD Thesis work. - Significant results have been achieved in the more accurate measurement of thermal material parameters. A publication dealing with this subject was given the IEEE CPMT Best Paper Award in 2006. - Significant results have been achieved in the qualification of the cooling properties of microchannel coolers. The results have been presented in 5 papers made in international cooperation

Testing of PLL-based True Random Number Generator in Changing Working Conditions

Security of cryptographic systems depends significantly on security of secret keys. Unpredictability of the keys is achieved by their generation by True Random Number Generators (TRNGs). In the paper we analyze behavior of the Phase-Locked Loop (PLL) based TRNG in changing working environment. The frequency of signals synthesized by PLL may be naturally influenced by chip temperature. We show what impact the temperature has on the quality of generated random sequence of the PLL-based TRNG. Thank to analysis of internal signals of the generator we are able to prove dependencies between the PLL parameters, statistical parameters of the generated sequence and temperature. Considering the measured results of experiments we form a new requirement in order to improve the robustness of the designed TRNG

An Improved Fault Tolerant Technique of Median Filter

Acquisition noises in the digital image processing system basically made out of imprudent clamors, for example, hot and dead pixels, and for the most part expelled utilizing middle channels. The median filtering algorithm can be speedup by FPGA implementation. Configuration memory cells in SRAM based FPGAs are susceptible to radiation effects such as SEUs which leads to configuration memory bit flips and hence a protective measure is required for the proper operation of median filtering algorithm.The fault tolerant implementations of median filter provides a range for median value with which the calculated median value is checked and find out error if the median is out of the provided range. The main aim of the project is to fasten up the fault tolerant implementation of median filter in FPGAs by adding a few resources. Experimental results show that the proposed technique significantly reduces the latency of the fault tolerant median filtering process

Run-time transmission power reconfiguration and adaptive packet relocation in wireless network-on-chip

Network-on-chip (NoC) is an on-chip communication network that allows parallel communication between all cores to improve inter-core performance. Wireless NoC (WiNoC) introduces long-range and high bandwidth radio frequency (RF) interconnects that can possibly reduce the multi-hop communication of the planar metal interconnects in conventional NoC platforms. In WiNoC, RF transceivers account for a significant power consumption, particularly its transmitter, out of its total communication energy. CurrentWiNoC architectures employ constant maximum transmitting power for communicating radio hubs regardless of physical location of the receiver radio hubs. Besides, high transmission power consumption in WiNoC with constant maximum power suffers from significant energy and load imbalance among RF transceivers which lead to hotspot formation, thus affecting the reliability of the onchip network system. There are two main objectives covered by this thesis. Firstly, this work proposes a reconfigurable transmitting power control scheme that, by using bit error rate (BER) estimation obtained at the receiver’s side, dynamically calibrates the transmitting power level needed for communication between the source and destination radio hubs. The proposed scheme achieves significant total system energy reduction by about 40% with an average performance degradation of 3% and with no impact on throughput. The proposed design utilizes a small fraction of both area and power overheads (about 0.1%) out of total transceiver properties. The proposed technique is generic and can be applied to any WiNoC architecture for improving its energy efficiency with a negligible overhead in terms of silicon area. Secondly, an energyaware adaptive packet relocator scheme has been proposed. Based on transmission energy consumption and predefined energy threshold, packets are routed to adjacent transmitter for communication with receiver radio hub, with an aim to balance energy distribution in WiNoC. The proposed strategy alone achieves total communication energy savings of about 8%. A joint scheme of the reconfigurable transmitting power management and energy-aware adaptive packet relocator is also introduced. The scheme consistently results in an energy savings of 30% with minimal performance degradation

Jitter Estimation with High Accuracy for Oscillator-Based TRNGs

Ring oscillator-based true random number generators (RO-based TRNGs) are widely used to provide unpredictable random numbers for cryptographic systems. The unpredictability of the output numbers, which can be measured by entropy, is extracted from the jitter of the oscillatory signal. To quantitatively evaluate the entropy, several stochastic models have been proposed, all of which take the jitter as a key input parameter. So it is crucial to accurately estimate the jitter in the process of entropy evaluation. However, several previous methods have estimated the jitter with non-negligible error, which would cause the overestimation of the entropy. In this paper, we propose a jitter estimation method with high accuracy. Our method aims at eliminating the quantization error in previous counter-based jitter estimation methods and finally can estimate the jitter with the error smaller than $1\%$. Furthermore, for the first time, we give a theoretical error bound for our jitter estimation. The error bound confirms the $1\%$ error level of our method. As a consequence, our method will signicantly help to evaluate the entropy of RO-based TRNGs accurately. Finally, we present the application of our jitter estimation method on a practical FPGA device and provide a circuit module diagram for on-chip implementation

ПСЕВДОИСЧЕРПЫВАЮЩЕЕ ТЕСТИРОВАНИЕ ЗАПОМИНАЮЩИХ УСТРОЙСТВ НА БАЗЕ МНОГОКРАТНЫХ МАРШЕВЫХ ТЕСТОВ

Methods for modern memory devices are analyzed. The validity of using pseudo-exhaustive tests to detect complex memory faults is shown. A necessary condition for generating a pseudo-exhaustive test for a given number of memory cells is formulated. It is shown that the problem of generating a pseudo-exhaustive test based on multiple memory tests with a variable background is reduced to the combinatorial task of the coupon collector. Estimates of the mean, minimum, and maximum multiplicity of a multiple test are given to provide an exhaustive set of combinations for a given number of cells of a memory device. The validity of analytical estimates is shown experimentally and the possibility of pseudo-exhaustive memory testing is confirmed.Анализируются методы тестирования современных запоминающих устройств. Показывается обоснованность применения псевдоисчерпывающих тестов для обнаружения сложных неисправностей памяти. Формулируется необходимое условие генерирования псевдоисчерпывающего теста для заданного количества ячеек запоминающего устройства. Показывается, что задача генерирования псевдоисчерпывающего теста на базе многократных тестов запоминающих устройств с изменяемым начальным состоянием сводится к комбинаторной задаче собирателя купонов. Приводятся оценки средней, минимальной и максимальной кратности многократного теста для обеспечения исчерпывающего множества комбинаций для заданного числа ячеек запоминающего устройства. Экспериментально показывается справедливость аналитических оценок и подтверждается возможность псевдоисчерпывающего тестирования запоминающих устройств.

Proposal of an Adaptive Fault Tolerance Mechanism to Tolerate Intermittent Faults in RAM

[EN] Due to transistor shrinking, intermittent faults are a major concern in current digital systems. This work presents an adaptive fault tolerance mechanism based on error correction codes (ECC), able to modify its behavior when the error conditions change without increasing the redundancy. As a case example, we have designed a mechanism that can detect intermittent faults and swap from an initial generic ECC to a specific ECC capable of tolerating one intermittent fault. We have inserted the mechanism in the memory system of a 32-bit RISC processor and validated it by using VHDL simulation-based fault injection. We have used two (39, 32) codes: a single error correction-double error detection (SEC-DED) and a code developed by our research group, called EPB3932, capable of correcting single errors and double and triple adjacent errors that include a bit previously tagged as error-prone. The results of injecting transient, intermittent, and combinations of intermittent and transient faults show that the proposed mechanism works properly. As an example, the percentage of failures and latent errors is 0% when injecting a triple adjacent fault after an intermittent stuck-at fault. We have synthesized the adaptive fault tolerance mechanism proposed in two types of FPGAs: non-reconfigurable and partially reconfigurable. In both cases, the overhead introduced is affordable in terms of hardware, time and power consumption.This research was supported in part by the Spanish Government, project TIN2016-81,075-R, and by Primeros Proyectos de Investigacion (PAID-06-18), Vicerrectorado de Investigacion, Innovacion y Transferencia de la Universitat Politecnica de Valencia (UPV), project 20190032.Baraza Calvo, JC.; Gracia-Morán, J.; Saiz-Adalid, L.; Gil Tomás, DA.; Gil, P. (2020). Proposal of an Adaptive Fault Tolerance Mechanism to Tolerate Intermittent Faults in RAM. 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ACM SIGPLAN Notices, 47(4), 111-122. doi:10.1145/2248487.2150989Gil-Tomás, D., Gracia-Morán, J., Baraza-Calvo, J.-C., Saiz-Adalid, L.-J., & Gil-Vicente, P.-J. (2012). Studying the effects of intermittent faults on a microcontroller. Microelectronics Reliability, 52(11), 2837-2846. doi:10.1016/j.microrel.2012.06.004Plasma CPU Modelhttps://opencores.org/projects/plasmaArlat, J., Aguera, M., Amat, L., Crouzet, Y., Fabre, J.-C., Laprie, J.-C., … Powell, D. (1990). Fault injection for dependability validation: a methodology and some applications. IEEE Transactions on Software Engineering, 16(2), 166-182. doi:10.1109/32.44380Gil-Tomas, D., Gracia-Moran, J., Baraza-Calvo, J.-C., Saiz-Adalid, L.-J., & Gil-Vicente, P.-J. (2012). Analyzing the Impact of Intermittent Faults on Microprocessors Applying Fault Injection. IEEE Design & Test of Computers, 29(6), 66-73. doi:10.1109/mdt.2011.2179514Rashid, L., Pattabiraman, K., & Gopalakrishnan, S. (2010). Modeling the Propagation of Intermittent Hardware Faults in Programs. 2010 IEEE 16th Pacific Rim International Symposium on Dependable Computing. doi:10.1109/prdc.2010.52Amiri, M., Siddiqui, F. M., Kelly, C., Woods, R., Rafferty, K., & Bardak, B. (2016). FPGA-Based Soft-Core Processors for Image Processing Applications. Journal of Signal Processing Systems, 87(1), 139-156. doi:10.1007/s11265-016-1185-7Hailesellasie, M., Hasan, S. R., & Mohamed, O. A. (2019). MulMapper: Towards an Automated FPGA-Based CNN Processor Generator Based on a Dynamic Design Space Exploration. 2019 IEEE International Symposium on Circuits and Systems (ISCAS). doi:10.1109/iscas.2019.8702589Mittal, S. (2018). A survey of FPGA-based accelerators for convolutional neural networks. Neural Computing and Applications, 32(4), 1109-1139. doi:10.1007/s00521-018-3761-1Intel Completes Acquisition of Alterahttps://newsroom.intel.com/news-releases/intel-completes-acquisition-of-altera/#gs.mi6ujuAMD to Acquire Xilinx, Creating the Industry’s High Performance Computing Leaderhttps://www.amd.com/en/press-releases/2020-10-27-amd-to-acquire-xilinx-creating-the-industry-s-high-performance-computingKim, K. H., & Lawrence, T. F. (s. f.). Adaptive fault tolerance: issues and approaches. [1990] Proceedings. Second IEEE Workshop on Future Trends of Distributed Computing Systems. doi:10.1109/ftdcs.1990.138292Gonzalez, O., Shrikumar, H., Stankovic, J. A., & Ramamritham, K. (s. f.). Adaptive fault tolerance and graceful degradation under dynamic hard real-time scheduling. Proceedings Real-Time Systems Symposium. doi:10.1109/real.1997.641271Jacobs, A., George, A. D., & Cieslewski, G. (2009). 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Reliability-Based ECC System for Adaptive Protection of NAND Flash Memories. 2015 Fifth International Conference on Communication Systems and Network Technologies. doi:10.1109/csnt.2015.23Zhou, Y., Wu, F., Lu, Z., He, X., Huang, P., & Xie, C. (2019). SCORE. ACM Transactions on Architecture and Code Optimization, 15(4), 1-25. doi:10.1145/3291052Lu, S.-K., Li, H.-P., & Miyase, K. (2018). Adaptive ECC Techniques for Reliability and Yield Enhancement of Phase Change Memory. 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS). doi:10.1109/iolts.2018.8474118Chen, J., Andjelkovic, M., Simevski, A., Li, Y., Skoncej, P., & Krstic, M. (2019). Design of SRAM-Based Low-Cost SEU Monitor for Self-Adaptive Multiprocessing Systems. 2019 22nd Euromicro Conference on Digital System Design (DSD). doi:10.1109/dsd.2019.00080Wang, X., Jiang, L., & Chakrabarty, K. (2020). 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Low Power CMOS Design : Exploring Radiation Tolerance in a 90 nm Low Power Commercial Process

This thesis aims to examine radiation tolerance of low power digital CMOS circuits in a commercial 90 nm low power triple-well process from TSMC. By combining supply voltage scaling and Radiation-Hardened By Design (RHBD) design techniques, the goal is to achieve low supply voltage, radiation tolerant, circuit behavior. The target circuit architecture for comparison between different radiation hardening techniques is a Successive Approximation Register (SAR) architecture comprising both combinational and sequential logic. The purpose of the SAR architecture is to emulate a larger system, since larger systems are usually composed of combinational and sequential building blocks. The method used for achieving low power operation is primarily voltage scaling, with the ultimate goal of reaching subthreshold operation, while maintaining radiation tolerant circuit behavior. Radiation hardening is performed on circuit-level by applying RHBD circuit topologies, as well as architectural-level mitigation techniques. This thesis includes three papers within the field of robust low power CMOS design. Two of the papers cover low power level shifter designs in 90 nm and 65 nm process from STMicroelectronics. The third paper examines memory element design using minority-3 gates and inverters for robust low voltage operation. Prototyping has been conducted on low power CMOS building blocks including level shifter and memory design, for potential use in future radiation tolerant designs. Prototyping has been conducted on two chips from two different 90 nm processes from STMicroelectronics and TSMC. A test setup for radiation induced errors has been developed. Experimental radiation tests of the SAR architectures were conducted at SAFE, revealing no radiation induced errors