Effect of drift region doping and coulmn thickness variations in a super junction power MOSFET: a 2-D simulation study

In this paper, a power SJMOSFET (Super junction MOSFET) transistor is simulated using PISCES-II, a 2-D numerical device simulator. The doping densities and device dimensions are chosen so as to simulate a typical device structure. These simulations are aimed at understanding the device physics through various electrical quantities like potential distribution, electric field distribution, and electron concentrations etc. in different regions of the device both in on/off states. The effects of doping variations in the ‘n’ and ‘p’ pillars of the SJMOSFET along with the variations in the column thickness of the device were investigated. Various results obtained reveal that device having equal doping in the n and p pillars and having equal width of these pillars gives the best results. The current density is maximum and the charge imbalance is minimum for this case, however the breakdown voltage increases when the width of the n pillar is decreased. When you are citing the document, use the following link http://essuir.sumdu.edu.ua/handle/123456789/2793

A high-efficiency super-junction MOSFET based inverter-leg configuration using a dual-mode switching technique

High-efficiency power converters have benefits of minimizing energy consumption, reducing costs, and realizing high power densities. The silicon super-junction MOSFET is an attractive device for high-efficiency applications. However, its highly non-linear output capacitance and the reverse recovery properties of its intrinsic diode must be addressed when used in voltage source converters. A dual-mode switching technique operating in conjunction with intrinsic diode deactivation circuitry is proposed in this paper. The technique is demonstrated in an 800-W inverter-leg configuration operating from a 400-V DC voltage rail and switching at 20 kHz. Intended applications include machine drives. The full-load efficiency reaches approximately 98.7% and no forced cooling is needed

Critical impact energy for local impact damage of hard projectile on concrete slab

Concrete is a common construction material used to build conventional, un�conventional, and sensitive structures. Great demand exists for efficient designing of concrete as protective structures against impact loading generated by natural disasters and consciously engendered unpleasant incidents etc. When hard projectile collides with concrete wall it is the impact energy of the projectile that makes concrete target to deform, which means impact energy is the dominant cause of damage in impact accidents. Hard missile impact can generate both local (penetration, scabbing, and perforation) and global impact damage. Local damage studies normally fall into three categories, i.e. empirical formulation, idealised analytical models, and numerical simulations. The present study is curiously focused on the required critical impact energy for occurrence of local impact damage in concrete structures generated by hard projectile, via three categories i). Numerical simulation, ii). Analytical modelling, and iii). Empirical formula The numerical simulations were conducted to determine the critical impact energy of ogive nose hard projectile which causes maximum penetration in to the concrete structures. The effects of diameter and CRH ratio of ogive nose hard projectile on critical impact energy were also analysed. An analytical model is developed to predict the required critical impact energy for spalling, tunnelling and penetration in concrete target. A nose shape factor (Ni) also has been introduced with empirical friction factor (Nf) in Chen and Li nose shape factor (N* ), to analyze the effects of nose shape on critical impact energy. Furthermore, an empirical formula also has been developed. The early stage scabbing phenomenon has been observed through the wave propagation in simulations with fully elastic model assumptions. The critical impact energy required for scabbing of concrete target and the effects of diameter of projectile (d) and the target thickness (H) on critical impact energy has been observed. An analytical model is developed based on 1-Dimensional with reflected wave propagation, and shear assumptions. Furthermore, an empirical formula also has been introduced. For perforation, the penetration numerical simulations have been further extended to achieve perforation in deep concrete against impact of ogive nose hard projectile with CRH = (3.0, 4.25, and 6.0). The required critical impact energy and residual impact energy has been analysed. Furthermore, the modifications in Li and Reid (2006) perforation model also have been done. In Addition a new empirical formula also has been introduced. The out come of this study can be used for making design recommendation and design procedures for determining the dynamic response of the concrete target to prevent local impact damag

High-efficiency voltage source converters with silicon super-junction MOSFETs

High-efficiency power converters have the benefits of minimising energy consumption, reducing costs, and realising high power densities. The silicon super-junction (SJ) MOSFET is an attractive device for high-efficiency applications. However, its highly non-linear output capacitance and the reverse recovery properties of its intrinsic diode must be addressed when used in voltage source converters (VSCs). The research in this thesis aims at addressing these two problems and realising high efficiency. Initially, state-of-art techniques in the literature are reviewed. In order to develop a solution with simple hardware, no major auxiliary magnetic components, and no onerous timing requirements, a dual-mode switching technique is proposed. The technique is demonstrated using a SJ MOSFET based bridge-leg circuit. The hardware performance is then experimentally investigated with different power semiconductor device permutations. The transition conditions between the two switching modes do not have to be tightly set in order to maintain a high efficiency. The dual-mode switching technique is then further investigated with a current transformer (CT) arrangement embedded in the MOSFET’s gate driver circuit in order to control the profile of the MOSFET’s incoming drain current at turn on. The dual-mode switching technique, with or without a CT scheme, is shown to achieve high efficiency with minimal additional hardware.High-efficiency power converters have the benefits of minimising energy consumption, reducing costs, and realising high power densities. The silicon super-junction (SJ) MOSFET is an attractive device for high-efficiency applications. However, its highly non-linear output capacitance and the reverse recovery properties of its intrinsic diode must be addressed when used in voltage source converters (VSCs). The research in this thesis aims at addressing these two problems and realising high efficiency. Initially, state-of-art techniques in the literature are reviewed. In order to develop a solution with simple hardware, no major auxiliary magnetic components, and no onerous timing requirements, a dual-mode switching technique is proposed. The technique is demonstrated using a SJ MOSFET based bridge-leg circuit. The hardware performance is then experimentally investigated with different power semiconductor device permutations. The transition conditions between the two switching modes do not have to be tightly set in order to maintain a high efficiency. The dual-mode switching technique is then further investigated with a current transformer (CT) arrangement embedded in the MOSFET’s gate driver circuit in order to control the profile of the MOSFET’s incoming drain current at turn on. The dual-mode switching technique, with or without a CT scheme, is shown to achieve high efficiency with minimal additional hardware

Modeling and Control of a Tapped-Inductor Buck Converter with Pulse Frequency Modulation

A tapped-inductor buck converter auxiliary power supply for cascaded converter submodules is modeled. Then, a closed loop output voltage control, which uses the switching frequency as control variable, is designed and implemented using a micro-controller. A prototype is built and tested. Finally, the start-up procedure of the converter is studied and achieve

Design and Development of Power Inverter using Combinational Switches for Improvement of Efficiency at Light Loads

For standalone residential power system Inverters are designed using peak load capacity keeping in mind. The efficiency of such inverter on light load is low. The efficiency of inverter can be improved in light load condition using switch combination in inverter. A comparative analysis of using different individual switching and combination devices will be carried out for specific load. A hardware realization of inverter for a specific capacity using most efficient switch combination will be done

Study of Novel Power Semiconductor Devices for Performance and Reliability.

Power Semiconductor Devices are crucial components in present day power electronic systems. The performance and efficiency of the devices have a direct correlation with the power system efficiency. This dissertation will examine some of the components that are commonly used in a power system, with emphasis on their performance characteristics and reliability. In recent times, there has a proliferation of charge balance devices in high voltage discrete power devices. We examine the same charge balance concept in a fast recovery diode and a MOSFET. This is crucial in the extending system performance at compact dimensions. At smaller device and system sizes, the performance trade-off between the ON and OFF states becomes all the more critical. The focus on reducing the switching losses while maintaining system reliability increases. In a conventional planar technology, the technology places a limit on the switching performance owing to the larger die sizes. Using a charge balance structure helps achieve the improved trade-off, while working towards ultimately improving system reliability, size and cost. Chapter 1 introduces the basic power system based on an inductive switching circuit, and the various components that determine its efficiency. Chapter 2 presents a novel Trench Fast Recovery Diode (FRD) structure with injection control is proposed in this dissertation. The proposed structure achieves improved carrier profile without the need for excess lifetime control. This substantially improves the device performance, especially at extreme temperatures (-40oC to 175oC). The device maintains low leakage at high temperatures, and it\u27s Qrr and Irm do not degrade as is the usual case in heavily electron radiated devices. A 1600 diode using this structure has been developed, with a low forward turn-on voltage and good reverse recovery properties. The experimental results show that the structure maintains its performance at high temperatures. In chapter 3, we develop a termination scheme for the previously mentioned diode. A major limitation on the performance of high voltage power semiconductor is the edge termination of the device. It is critical to maintain the breakdown voltage of the device without compromising the reliability of the device by controlling the surface electric field. A good termination structure is critical to the reliability of the power semiconductor device. The proposed termination uses a novel trench MOS with buried guard ring structure to completely eliminate high surface electric field in the silicon region of the termination. The termination scheme was applied towards a 1350 V fast recovery diode, and showed excellent results. It achieved 98% of parallel plane breakdown voltage, with low leakage and no shifts after High Temperature Reverse Bias testing due to mobile ion contamination from packaging mold compound. In chapter 4, we also investigate the device physics behind a superjunction MOSFET structure for improved robustness. The biggest issue with a completely charge balanced MOSFET is decreased robustness in an Unclamped Inductive Switching (UIS) Circuit. The equally charged P and N pillars result in a flat electric field profile, with the peak carrier density closer to the P-N junction at the surface. This results in an almost negligible positive dynamic Rds-on effect in the MOSFET. By changing the charge profile of the P-column, either by increasing it completely or by implementing a graded profile with the heavier P on top, we can change the field profile and shift the carrier density deeper into silicon, increasing the positive dynamic Rds-on effect. Simulation and experimental results are presented to support the theory and understanding. Chapter 5 summarizes all the theories presented and the contributions made by them in the field. It also seeks to highlight future work to be done in these areas