On-line Testing Field Programmable Analog Array Circuits

This work presents an efficient methodology to on-line test field programmable analog array (FPAA) circuits. It proposes to partition the FPAA circuit under test into sub circuits. Each sub circuit is tested by replicating the sub circuit with programmable resources on FPAAs, and comparing the outputs of the original partitioned sub circuit and its replication. The advantages of this approach includes: low implementation cost, enhanced testability, and flexible testing schedules. This work also presents circuit techniques to address stability problems which are often encountered in the proposed on-line testing approach. In addition, the impact of performing circuit partition on testability is investigated in this work. It shows that testability is generally improved in partitioned circuits. Finally, experimental results are presented to demonstrate the feasibility and effectiveness of the proposed techniques

Novel CCII-based Field Programmable Analog Array and its Application to a Sixth-Order Butterworth LPF

In this paper, a field programmable analog array (FPAA) is proposed. The proposed FPAA consists of seven configurable analog blocks (CABs) arranged in a hexagonal lattice such that the CABs are directly connected to each other. This structure improves the overall frequency response of the chip by decreasing the parasitic capacitances in the signal path. The CABS of the FPAA is based on a novel fully differential digitally programmable current conveyor (DPCCII). The programmability of the DPCCII is achieved using digitally controlled three-bit MOS ladder current division network. No extra biasing circuit is required to generate specific analog control voltage signals. The DPCCII has constant standby power consumption, offset voltage, bandwidth and harmonic distortions over all its programming range. A sixth-order Butterworth tunable LPF suitable for WLAN/WiMAX receivers is realized on the proposed FPAA. The filter power consumption is 5.4mW from 1V supply; it’s cutoff frequency is tuned from 5.2 MHz to 16.9 MHz. All the circuits are realized using 90nm CMOS technology from TSMC. All simulations are carried out using Cadence

Application of the FPAA to Sample Input Signal for Laboratory Exercise: Pulse Amplitude Modulation

This paper presents exemplary exercise on the fundamentals of signal processing course which is offered for second year bachelor level students. Application of Field Programmable Analog Array (FPAA) for pulse amplitude modulation (PAM) exercise is described with signal processing laboratory. There are presented two methods for implementing PAM modulation and demodulation technique in FPAA module. Example configuration files are available form Authors’ web site

A wideband linear tunable CDTA and its application in field programmable analogue array

This document is the Accepted Manuscript version of the following article: Hu, Z., Wang, C., Sun, J. et al. ‘A wideband linear tunable CDTA and its application in field programmable analogue array’, Analog Integrated Circuits and Signal Processing, Vol. 88 (3): 465-483, September 2016. Under embargo. Embargo end date: 6 June 2017. The final publication is available at Springer via https://link.springer.com/article/10.1007%2Fs10470-016-0772-7 © Springer Science+Business Media New York 2016In this paper, a NMOS-based wideband low power and linear tunable transconductance current differencing transconductance amplifier (CDTA) is presented. Based on the NMOS CDTA, a novel simple and easily reconfigurable configurable analogue block (CAB) is designed. Moreover, using the novel CAB, a simple and versatile butterfly-shaped FPAA structure is introduced. The FPAA consists of six identical CABs, and it could realize six order current-mode low pass filter, second order current-mode universal filter, current-mode quadrature oscillator, current-mode multi-phase oscillator and current-mode multiplier for analog signal processing. The Cadence IC Design Tools 5.1.41 post-layout simulation and measurement results are included to confirm the theory.Peer reviewedFinal Accepted Versio

A Methodology to Perform Online Self-Testing for Field-Programmable Analog Array Circuits

This paper presents a methodology to perform online self-testing for analog circuits implemented on field-programmable analog arrays (FPAAs). It proposes to partition the FPAA circuit under test into subcircuits. Each subcircuit is tested by replicating the subcircuit with programmable resources on the FPAA chip, and comparing the outputs of the subcircuit and its replication. To effectively implement the proposed methodology, this paper proposes a simple circuit partition method and develops techniques to address circuit stability problems that are often encountered in the proposed testing method. Furthermore, error sources in the proposed testing circuit are studied and methods to improve the accuracy of testing results are presented. Finally, experimental results are presented to demonstrate the validity of the proposed methodology

The Analogue Computer as a Voltage-Controlled Synthesiser

This paper re-appraises the role of analogue computers within electronic and computer music and provides some pointers to future areas of research. It begins by introducing the idea of analogue computing and placing in the context of sound and music applications. This is followed by a brief examination of the classic constituents of an analogue computer, contrasting these with the typical modular voltage-controlled synthesiser. Two examples are presented, leading to a discussion on some parallels between these two technologies. This is followed by an examination of the current state-of-the-art in analogue computation and its prospects for applications in computer and electronic music

Wireless Cloud Architecture Based on Thin Clients and Ontologies

Recently, several researchers have discovered the need for radios to use description techniques for the objects in the wireless realm. The concept of RF field-programmable analog array (FPAA) was also proposed recently and the lack of hardware abstractions was identified as a problem. We propose a hardware abstraction for RF FPAAs, which enables an open RF-digital interface. We advance the concept of wireless thin clients. These clients are connected to the cloud using the open RF-digital interface. We describe the architecture of a comprehensive wireless ontology

Evolving circuits on a field programmable analog array using genetic programming

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.Includes bibliographical references (p. 57-60).This thesis describes the design and implementation of the Genetic Programming Intrinsic Circuit (GPIC) design system. Inspired by a number of recent advances in the field of Evolvable Hardware, the intended purpose of GPIC is to automate the design of analog circuits with minimal domain knowledge, computational resources, and cost using Genetic Programming with candidate solutions implemented in real hardware. This system has been constructed out of commercially available hardware and software, and the components were integrated through the development of a modular device-independent software system. The fitness evaluations of the candidate solutions of the Genetic Programming module are realized through a C interface to a National Instruments Data Acquisition Card. This Genetic Programming approach to analog circuit design decreases the fitness evaluation time of previous approaches by substituting expensive circuit simulation for real-time hardware testing. Since performing fitness evaluations in simulation is limited by the known model for a given environment, intrinsic testing provides additional benefit through the inherent incorporation of any unknown environmental conditions during tests. This feature is especially important for autonomous systems in unknown environments, and systems that must perform well in extreme environments.by Michael A. Terry.M.Eng