Evaluation of DyScO(x) as an alternative blocking dielectric in TANOS memories with Si(3)N(4) or Si-rich SiN charge trapping layers

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Flash Memory Devices

Flash memory devices have represented a breakthrough in storage since their inception in the mid-1980s, and innovation is still ongoing. The peculiarity of such technology is an inherent flexibility in terms of performance and integration density according to the architecture devised for integration. The NOR Flash technology is still the workhorse of many code storage applications in the embedded world, ranging from microcontrollers for automotive environment to IoT smart devices. Their usage is also forecasted to be fundamental in emerging AI edge scenario. On the contrary, when massive data storage is required, NAND Flash memories are necessary to have in a system. You can find NAND Flash in USB sticks, cards, but most of all in Solid-State Drives (SSDs). Since SSDs are extremely demanding in terms of storage capacity, they fueled a new wave of innovation, namely the 3D architecture. Today “3D” means that multiple layers of memory cells are manufactured within the same piece of silicon, easily reaching a terabit capacity. So far, Flash architectures have always been based on "floating gate," where the information is stored by injecting electrons in a piece of polysilicon surrounded by oxide. On the contrary, emerging concepts are based on "charge trap" cells. In summary, flash memory devices represent the largest landscape of storage devices, and we expect more advancements in the coming years. This will require a lot of innovation in process technology, materials, circuit design, flash management algorithms, Error Correction Code and, finally, system co-design for new applications such as AI and security enforcement

Nitrided GdTiO as charge-trapping layer for flash memory applications

Based on capacitor with the structure of Al/Al2O 3/GdTiO (N)/SiO2/Si, the charge-trapping properties of GdTiO and GdTiON films were investigated. Compared to the memory device with GdTiO film as charge-trapping layer, the one with GdTiON showed higher program/erase speed, larger memory window, and better retention characteristic due to additional charge traps with desirable energy level created by nitrogen incorporation in the film. © 2012 IEEE.published_or_final_versio

Fabrication and electrical characterization of MONOS memory with novel high-κ gate stack

A novel high-κ gate stack structure with HfON/SiO 2 as dual tunneling layer (DTL), AIN as charge storage layer (CSL) and HfAIO as blocking layer (BL) is proposed to prepare the charge-trapping type of MONOS non-volatile memory device by employing in-situ sputtering method. The memory window, program/erase and retention properties are investigated and compared with similar gate stack structure with Si 3N 4/SiO 2 as DTL, HfO 2 as CSL and Al 2O 3 as BL. Results show a large memory window of 3.55 V at PIE voltage of +8 V/-I5 V, high program/erase speed and good retention characteristic can be achieved using the novel Au/ HfAIO/AIN/(HfON/SiO 2)/Si gate stack structure. The main mechanisms lie in the enhanced electron injection through the high-κ HfON/SiO 2 DTL, high trapping efficiency of the high-κ AIN material and effective blocking role of the high-κ HfAIO BL. ©2009 IEEE.published_or_final_versionThe IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) 2009, Xi'an, China, 25-27 December 2009. In Proceedings of EDSSC, 2009, p. 521-52

Mutual fund performance: banking versus independent managers

We examine the performance of mutual fund managers for a sample of Spanish mutual funds considering data on active management, loads, size and the number of funds managed per manager. We find evidence of differences in fund performance according to management: independent managers outperform their banking counterparts even when the lower associated fees are considered. Overall, our results suggest that superior active managers do exist and the slight discrepancies which arise between managers can be interpreted as agency problems

Design and Evaluation of a Sub-1-Volt Read Flash Memory in a Standard 130 Nanometer CMOS Process

Nonvolatile memory design is a discipline that employs digital and analog circuit design techniques and requires knowledge of semiconductor physics and quantum mechanics. Methods for programming and erasing memory are discussed here, and simulation models are provided for Impact Hot Electron Injection (IHEI), Fowler-Nordheim (FN) tunneling, and direct tunneling. Extensive testing of analog memory cells was used to derive a set of equations that describe the oating-gate characteristics. Measurements of charge retention also revealed several leakage mechanisms, and methods for mitigating leakage are presented. Fabrication of ash memory in a standard CMOS process presents significant design challenges. The absence of multiple polysilicon layers requires that additional devices be used to control the oating-gate voltage. Furthermore high-voltage devices are often required to isolate the selected memory cells during write and erase cycles. However, a single-poly design allows portability to another standard process provided that the oating-gate characteristics are known. A ash memory system is presented here that has been fabricated in a standard 130 nanometer CMOS process. The design utilizes capacitive feedback to maintain desired injection current during programming. It also includes a sense amplifier design which features auto-zeroing of inherent offsets. Comparisons to existing memory designs show that a significant improvement in areal density was achieved through the elimination of on-die high-voltage charge pumps and switches. Measurements were performed over a range of clock frequencies and supply voltages. Results show that this memory system is capable of a read access time of 3.5 microseconds with a 1 megahertz clock while consuming less than 25 microwatts from a 1 volt supply. Operation down to 650 millivolts was confirmed where power consumption was reduced to only 3.4 microwatts. The low power consumption and high density of this ash memory make it an excellent choice for on-die firmware storage in battery-powered embedded applications

Improved Charge-Trapping Properties of TiON/HfON Dual Charge Storage Layer by Tapered Band Structure

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Influence of deposition conditions on charge-trapping based nonvolatile memories

Ankara : The Department of Electrical and Electronics Engineering and The Graduate School of Engineering and Science of Bilkent University, 2014.Thesis (Master's) -- Bilkent University, 2014.Includes bibliographical references leaves 36-38.Ghauri, Muhammad MaizM.S

Comprehensive numerical simulation of threshold-voltage transients in nitride memories

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