Операция деления для параллельных вычислительных систем. Ч. 2

Предлагается цифровой метод выполнения арифметической операции деления (ОД). Алгоритм обеспечивает распараллеливание вычислительного процесса, ускорение его и повышение точности ОД. Он основан на выполнении этапов операций в алгебре матриц и реализации методов цифровой арифметики в булевой (возможно многозначной) алгебре. Рассмотрены варианты выполнения ОД и примеры решения. Предполагает развитие аналогичных работ в плане создания и использования комбинированных алгоритмов обработки данных путём применения других алгебр в сочетании с методами цифровой арифметики.Пропонується цифровий метод виконання арифметичної операції ділення (ОД). Алгоритм забезпечує розпаралелювання обчислювального процесу, прискорення його і підвищення точності. Він заснований на виконанні етапів операцій в алгебрі матриць і реалізації методів цифрової арифметики в булевій (можливо, у багатозначній) алгебрі. Розглянуто варіанти виконання операції та приклади рішення. Передбачає розвиток аналогічних робіт у плані створення і використання комбінованих алгоритмів обробки даних шляхом застосування інших алгебр у поєднанні з методами цифрової арифметики.It is proposed the digital method of performing arithmetic division operations (OD). Algorithm provides the parallelizing of computational process, its acceleration and improved accuracy. It is based on carrying out the steps of operations in the matrix algebra and realization of digital arithmetic in Boolean (possibly multi-valued) algebra. The variants of the execution of operation and examples of solutions are regarded. It is suggested the development of similar projects for the creation and using combined data processing algorithms by applying other algebras in combination with the digital arithmetic methods

Операция деления для параллельных вычислительных систем. Ч. 1

Предлагается цифровой метод выполнения арифметической операции деления (ОД). Алгоритм обеспечивает распараллеливание вычислительного процесса, ускорение его и повышение точности ОД. Он основан на выполнении этапов операций в алгебре матриц и реализации методов цифровой арифметики в булевой (возможно, многозначной) алгебре. Рассмотрены варианты выполнения ОД и примеры решения. Предполагается развитие аналогичных работ в плане создания и использования комбинированных алгоритмов обработки данных путём применения других алгебр в сочетании с методами цифровой арифметики.Пропонується цифровий метод виконання арифметичної операції ділення (ОД). Алгоритм забезпечує розпаралелювання обчислювального процесу, прискорення його і підвищення точності. Він заснований на виконанні етапів операцій в алгебрі матриць і реалізації методів цифрової арифметики в булевій (можливо, у багатозначній) алгебрі. Розглянуто варіанти виконання операції та приклади рішення. Передбачається розвиток аналогічних робіт у плані створення і використання комбінованих алгоритмів обробки даних шляхом застосування інших алгебр у поєднанні з методами цифрової арифметики.It is proposed the digital method of performing arithmetic division operations (DO). Algorithm provides the parallelizing of computing process, its acceleration and accuracy increase. It is based on carrying out the steps of operations in the matrix algebra and realization of digital arithmetic in Boolean (possibly multi-valued) algebra. Variants of the execution of operation and examples of solutions are regarded. The development of similar projects for the creation and use of combined data processing algorithms by applying other algebras in combination with the methods of digital arithmetic is suggested

When Chaos Meets Computers

This paper focuses on an interesting phenomenon when chaos meets computers. It is found that digital computers are absolutely incapable of showing true long-time dynamics of some chaotic systems, including the tent map, the Bernoulli shift map and their analogues, even in a high-precision floating-point arithmetic. Although the results cannot directly generalized to most chaotic systems, the risk of using digital computers to numerically study continuous dynamical systems is shown clearly. As a result, we reach the old saying that "it is impossible to do everything with computers only".Comment: 7 pages, 5 figure

Decimal ALU

The decimal number system is used in many commercial applications, such as financial analysis, banking, tax calculation, currency conversion, insurance and accounting. With the explosively increasing amount the data to be proposed, computers are introduced to help deal with it. However, in digital Arithmetic Logic Unit (ALU) circuit systems, the binary number system is widely used for its simplicity and easy realization in physical layout. This project aims at constructing an ALU that contains decimal additions, subtractions and multiplications using binary coded decimal (BCD) on a binary system platform

Study on bit parallel and serial arithmetic logic approaches

Abstract. This paper provides general overview of how computers process numbers and how computers do arithmetic. Different ways to implement digital arithmetic logic are presented. Bit-serial designs can save chip real estate, but require more clock cycles for arithmetic operations such as additions and multiplications. Bit-parallel designs produce results with fewer clock cycles, but require more gates, e.g., due to carry-look-ahead generators. This may translate into higher power dissipation. This BSc thesis presents an exploration of bit-serial-parallel and bit-parallel arithmetic logic designs. The intention is to gain understanding of their basic design characteristics

Vector processing-aware advanced clock-gating techniques for low-power fused multiply-add

The need for power efficiency is driving a rethink of design decisions in processor architectures. While vector processors succeeded in the high-performance market in the past, they need a retailoring for the mobile market that they are entering now. Floating-point (FP) fused multiply-add (FMA), being a functional unit with high power consumption, deserves special attention. Although clock gating is a well-known method to reduce switching power in synchronous designs, there are unexplored opportunities for its application to vector processors, especially when considering active operating mode. In this research, we comprehensively identify, propose, and evaluate the most suitable clock-gating techniques for vector FMA units (VFUs). These techniques ensure power savings without jeopardizing the timing. We evaluate the proposed techniques using both synthetic and “real-world” application-based benchmarking. Using vector masking and vector multilane-aware clock gating, we report power reductions of up to 52%, assuming active VFU operating at the peak performance. Among other findings, we observe that vector instruction-based clock-gating techniques achieve power savings for all vector FP instructions. Finally, when evaluating all techniques together, using “real-world” benchmarking, the power reductions are up to 80%. Additionally, in accordance with processor design trends, we perform this research in a fully parameterizable and automated fashion.The research leading to these results has received funding from the RoMoL ERC Advanced Grant GA 321253 and is supported in part by the European Union (FEDER funds) under contract TTIN2015-65316-P. The work of I. Ratkovic was supported by a FPU research grant from the Spanish MECD.Peer ReviewedPostprint (author's final draft

Real-time simulation of jet engines with digital computer. 1: Fabrication and characteristics of the simulator

The fabrication and performance of a real time jet engine simulator using a digital computer are discussed. The use of the simulator in developing the components and control system of a jet engine is described. Comparison of data from jet engine simulation tests with actual engine tests was conducted with good agreement

Measuring Improvement when Using HUB Formats to Implement Floating-Point Systems under Round-to-Nearest

MEC bajo TIN2013-42253-PThis paper analyzes the benefits of using HUB formats to implement floating-point arithmetic under round-tonearest mode from a quantitative point of view. Using HUB formats to represent numbers allows the removal of the rounding logic of arithmetic units, including sticky-bit computation. This is shown for floating-point adders, multipliers, and converters. Experimental analysis demonstrates that HUB formats and the corresponding arithmetic units maintain the same accuracy as conventional ones. On the other hand, the implementation of these units, based on basic architectures, shows that HUB formats simultaneously improve area, speed, and power consumption. Specifically, based on data obtained from the synthesis, a HUB single-precision adder is about 14% faster but consumes 38% less area and 26% less power than the conventional adder. Similarly, a HUB single-precision multiplier is 17% faster, uses 22% less area, and consumes slightly less power than conventional multiplier. At the same speed, the adder and multiplier achieve area and power reductions of up to 50% and 40%, respectively