Experiencia de renovación metodológica en la enseñanza de la electrónica digital básica

Esta contribución presenta una experiencia sobre el proceso de adaptación de una asignatura de electrónica digital básica de primer curso de la titulación de Ingeniería Informática impartida por los autores en uno de sus grupos, con motivo de la implantación de los nuevos títulos de grado. El grupo tiene la particularidad de impartirse en inglés dentro de una experiencia pionera en la Universidad de Sevilla. Aparte de esta singularidad, se han introducido profundas reformas tanto en el enfoque de los contenidos como en la metodología de enseñanza/aprendizaje y en la forma de evaluación. En la contribución, los autores analizan los resultados obtenidos como consecuencia de los cambios metodológicos introducidos teniendo en cuenta los resultados académicos, la opinión de los alumnos y la apreciación de los propios profesores

Minimalistic SDHC-SPI hardware reader module for boot loader applications

This paper introduces a low-footprint full hardware boot loading solution for FPGA-based Programmable Systems on Chip. The proposed module allows loading the system code and data from a standard SD card without having to re-program the whole embedded system. The hardware boot loader is processor independent and removes the need of a software boot loader and the related memory resources. The hardware overhead introduced is manageable, even in low-range FPGA chips, and negligible in mid- and high-range devices. The implementation of the SD card reader module is explained in detail and an example of a multi-boot loader is offered as well. The multi-boot loader is implemented and tested with the Xilinx's Picoblaze microcontroller

NanoFS: a hardware-oriented file system

NanoFS is a novel file system for embedded systems and storage-class memories (like flash) and is specially designed to be directly implemented in hardware. NanoFS is based on an original internal layout intended to achieve an optimal hardware implementation of the file system’s file lookup and data fetch operations. File system spe-cification on a sample reader module completely implemented in a pro-grammable device is introduced

Automated performance evaluation of skew-tolerant clocking schemes

In this paper the authors evaluate the timing and power performance of three skew-tolerant clocking schemes. These schemes are the well known master–slave clocking scheme (MS) and two schemes developed by the authors: Parallel alternating latches clocking scheme (PALACS) and four-phase parallel alternating latches clocking scheme (four-phase PALACS). In order to evaluate the timing performance, the authors introduce algorithms to obtain the clock waveforms required by a synchronous sequential circuit. Separated algorithms were developed for every clocking scheme. From these waveforms it is possible to get parameters such as the non-overlapping time and the clock period. They have been implemented in a tool and have been used to compare the timing performance of the clocking schemes applied to a simple circuit. To analyse the power consumption the authors have electrically simulated a simple circuit for several operation frequencies. The most remarkable conclusion is that it is possible to save about 50% of the power consumption of the clock distribution network by using PALACS.Ministerio de Ciencia y Tecnología TEC 2004-00840/MI

Digital Data Processing Peripheral Design for an Embedded Application based on the Microblaze Soft Core

In this paper we present a design of a peripheral for MicroBlaze soft core processor as part of a R+D project carried out in cooperation with three different companies. The objective of the project consisted in the development of an embedded system with a SoC implemented on a FPGA custom-designed board. This work addresses the design of a Digital Data Processing peripheral included as a part of the target SoC application, that process digital signals via the digital inputs on a proposed board. Peripheral functionality is configurable for each digital signal independently and is configured from the software running on the MicroBlaze processor core.Ministerio de Educación y Cultura TEC2007-61802/MICJunta de Andalucía EXC-2005-TIC-102

Building a basic membrane computer

In this work, we present the building of two well-known membrane com- puters (squares generator and divisor test). Although they are very basic machines they present problems common to every P system (competition, parallel execution of rules, membrane dissolution, etc.) that have to be solved in order to get real emulations for them. The presented designs mimic the systems operation in a realistic way, by achieving both maximum parallelism and non-determinism, and demonstrating for the rst time that a membrane computer can actually be built in silico. Our architectures fully emu- late the membranes behaviour yielding to a performance of one transition per clock cycle, supposing a real physical realization of the mentioned machines

Implementation of a FFT/IFFT Module on FPGA: Comparison of Methodologies

In this work, we have compared three different methodologies for the implementation of a FFT/IFFT module on FPGA: VHDL coding (VC), System-level tools at RT level (STR), and System-level tools at macroblock level (STM). In terms of resource usage and operation frequency, STM has obtained interesting results, although it has an important restriction about internal data width which produces a mean output error of 2.1%. VC and STR become a more general alternative that yields to a lower mean error (1.0%). Thus, we propose to combine VC and STR in order to facilitate the design process as well as allow designers to maintain total control over the module internal architecture and obtain an efficient structure

Introducción de dispositivos programables en prácticas de laboratorio

En esta comunicación se presenta la realización de una práctica de la asignatura Estructura de Computadores de primer curso de Ingeniería Informática en la que introduce el uso de dispositivos programables. En dicha práctica se realiza un multiplicador secuencial 4x4, diseñándolo con la herramienta ISE WebPack de Xilinx e implementándolo con placas de desarrollo de Xilin

Long-term on-chip verification of systems with logical events scattered in time

Traditional on-chip and off-chip logic analyzers present important shortcomings when used for the longterm verification of industrial embedded systems, forcing the designer to implement ad hoc verification solutions. This paper introduces a suitable solution for long-term verification of FPGA-based designs consisting of a verification core that uses the PicoBlaze microcontroller, dedicated logic and a serial port communication in order to monitor the internal signals of the system in a continuous way. The core design focuses on low resource requirements and has been successfully applied to the verification of a real industrial synchronization platform showing remarkable advantages over commercial on-chip solutions like Xilinx’s ChipScope Pro. Moreover, in order to improve the reusability of this core a software tool has been developed to automatically include the verification core in any specific system.Ministerio de Educación y Ciencia TEC2007-61802/MI

Signal Sampling Based Transition Modeling for Digital Gates Characterization

Es una ponencia del Congreso: PATMOS 2004 : 14th International Workshop on Power and Timing Modeling, Optimization and Simulation. ISBN: 978-3-540-23095-3Current characterization methods introduce an important error in the measurement process. In this paper, we present a novel method to drive the timing characterization of logic gates under variable input transition times. The method is based on sampling and scaling realistic transition waveforms and it is easy to implement and introduces negligible computational overhead in the characterization process. We show how models characterized using the proposed method may improve accuracy from 5% to 8%.Ministerio de Ciencia y Tecnología VERDI TIC 2002-2283Ministerio de Educación, Cultura y Deporte / Secretaría de Estado de Educación y Universidades / Dirección General de Universidades PHB2002-0018-P