In this work, we have compared three different methodologies for the implementation of a FFT/IFFT module on FPGA: VHDL coding (VC), System-level tools at RT level (STR), and System-level tools at macroblock level (STM). In terms of resource usage and operation frequency, STM has obtained interesting results, although it has an important restriction about internal data width which produces a mean output error of 2.1%. VC and STR become a more general alternative that yields to a lower mean error (1.0%). Thus, we propose to combine VC and STR in order to facilitate the design process as well as allow designers to maintain total control over the module internal architecture and obtain an efficient structure

Bellido Díaz, Manuel Jesús

Millán Calderón, Alejandro

Muñoz Rivera, Alejandro

Ostúa Arangüena, Enrique

Ruiz de Clavijo Vázquez, Paulino

Viejo Cortés, Julián

English

idUS. Depósito de Investigación Universidad de Sevilla

IMPLEMENTATION OF A FFT/IFFT MODULE ONFPGA: COMPARISON OF METHODOLOGIESJ. Viejo, A. Millan, M. J. Bellido, E. Ostua, P. Ruiz-de-Clavijo, and A. MunozGrupo ID2 (Investigacion y Desarrollo Digital)Departamento de Tecnologia Electronica-Universidad de SevillaE. T. S. Ing. Informatica, Campus Universitario Reina MercedesSevilla 41012 (SPAIN)Email: {julian, amillan, bellido, ostua, paulino, amrivera} @dte.us.esABSTRACTIn this work, we have compared three different method-ologies for the implementation of a FFT/IFFT module onFPGA: VHDL coding (VC), System-level tools at RT level(STR), and System-level tools at macroblock level (STM).In terms of resource usage and operation frequency, STMhas obtained interesting results, although it has an importantrestriction about internal data width which produces a meanoutput error of 2.1%. VC and STR become a more generalalternative that yields to a lower mean error (1.0%). Thus,we propose to combine VC and STR in order to facilitate thedesign process as well as allow designers to maintain totalcontrol over the module internal architecture and obtain anefficient structure.1. INTRODUCTIONThis work is included inside the design and implementa-tion of a modem based on the Orthogonal Frequency Divi-sion Multiplexing (OFDM) modulation/demodulation sys-tem [1]. For both processes of modulation and demodula-tion, it is required to calculate the Discrete Fourier Trans-form of the data (in both direct and inverse ways). Thus,a FFT/IFFT module becomes an essential part of the sys-tem. The implemented system processes 64-sample com-plex symbols using 26-bit data (13 bits for the real part and13 bits for the imaginary one).In previous works, we have presented the design and im-plementation of the system on FPGA (Field ProgrammableGate Array) [2] and ASIC (Application Specific IntegratedCircuit) [3]. These implementations were performed byusing a methodology based on coding in VHDL (VHSICHardware Description Language) [4]. However, it was veryimportant to evaluate the usefulness of the system-levelThis work has been partially supported by the Spanish Government'sMEC HIPER project TEC2007-61802/MIC and the Andalusian RegionalGovernment's EXC-2005-TIC-1023 project.tools provided by the FPGA foundry in order to improvesuch implementations. Thus, the objectives of the currentwork were: (a) perform a comparison between the VHDLcoding and the system-level tools approach and (b) proposea set of steps which summarize the best way to carry out thedesign process depending on the type of system.The system-level tools approach allows designers towork at different abstraction levels. So, the first objectiveactually involved the comparison of three methodologies:1. VHDL coding (VC): the system architecture isdesigned at RT (Register Transfer) level and imple-mented by direct coding in VHDL.2. System-level tools at RT level (STR): the system ar-chitecture is designed at RTL and implemented usingthe system-level tools provided by the FPGA foundry.Specifically, we have used System Generator for DSP(Digital Signal Processing) v8.2 from Xilinx [5].3. System-level tools at macroblock level (STM): theFFT/IFFT module is implemented using the FFTmacroblock provided by System Generator which canalso calculate the IFFT.The rest of the paper is organized as follows: in the nextsection the three methodologies used are described, the thirdsection presents the main results for both the simulation andthe implementation processes, in the fourth section these re-sults are discussed and a general methodology is proposed,and finally some conclusions are derived.2. DESIGN METHODOLOGIES FORIMPLEMENTATION ON FPGAAs we have mentioned previously, our aim was to evaluatethe effectiveness of System Generator for DSP. The work-flow we have used is conformed of three stages (Fig. 1):978-1-4244-1992-0/08/$25.00 C)2008 IEEE 7Authorized licensed use limited to: Universidad de Sevilla. Downloaded on January 11,2021 at 15:00:28 UTC from IEEE Xplore.  Restrictions apply. Fig. 1. Design and implementation workflow.1. Design: this stage differs from one methodology toanother and it is explained on the next.2. Synthesis and implementation: this stage is carriedout by using ISE v8.2i from Xilinx. Moreover, themodule operation, considering gate delay, is testedby post-P&R (Placement and Routing) simulationthrough ModelSim v6.0 from Mentor Graphics.3. Programming: finally, the device is configured by us-ing iMPACT v8.2i from Xilinx.Because the design stage depends on the methodologyused, a detailed explanation of each case is presented on thenext subsections.2.1. VHDL coding methodologyThe VC methodology consists of developing the FFT/IFFTmodule at RT level using VHDL language and followingthe usual methodology for digital system design (based on acontrol unit and a data path). The architecture of the mod-ule has been suited to the algorithm presented in [3] and isdepicted in Fig. 2. In this diagram, the most important com-ponent is the RADIX-8 butterfly that performs an 8-elementDFT in a parallel way and its implementation follows thestructure proposed in [6]. Around this main element, thereare several components which are described on the next:* CONJs. These components carry out the conjugateoperation of the complex data. Conjugators only op-erate in the IFFT case.* RAM. This memory stores the intermediate calcula-tions.* ROM. This block supplies the twiddle values (precal-culated).* TWIDDLE. The output data of the RADIX-8 compo-nent are multiplied by the corresponding twiddle val-ues at this component.* CONTROL UNIT. This unit is in charge of control-ling the whole process and has been designed as a fi-nite state machine according to the canonic structuredescribed in [7].8Authorized licensed use limited to: Universidad de Sevilla. Downloaded on January 11,2021 at 15:00:28 UTC from IEEE Xplore.  Restrictions apply. CLK RSTz CLEAR NTCONTROLUNIT3 3WRT OW SEL VALD FTCON MUX DATA OUT FFTCLK WRT ROW CLK WRT SE ROWFig. 2. Internal structure of the FFT/IFFT module.A more detailed explanation on the structure and func-tioning of the VHDL implementation can be found in [2, 3].Also, verification of such designs is usually carried outby using a VHDL simulator like ModelSim. However, an-other alternative has been explored in this work: the VHDLcode has been simulated using Simulink and ModelSimtogether (HDL co-simulation). That is possible throughthe System Generator's BLACK BOX block which allowsdesigners to import VHDL code into a System Generatordesign. In this type of verification, System Generator'sblocks are simulated through Simulink and the VHDLblocks (black boxes) are simulated through ModelSim.2.2. System-level tools at RTL methodologyThe STR methodology described in this work consists ofdesigning the FFT/IFFT module using System Generatorfor DSP: a tool developed by Xilinx that facilitates the de-sign and implementation of DSP functions on its FPGAs.This tool is a software platform integrated within Matlaband Simulink, from The MathWorks, and allows the designof DSP systems using the Xilinx BlockSet [8]. Also, it han-dles the automatic generation of VHDL code; synthesizableon Xilinx FPGAs.Within this methodology, the same module architectureemployed in the VC case has been applied. In this case,the data path has been built with the System Generator'sblocks and the same control unit has been added to the de-sign through the BLACK BOX block. Most of the sys-tem simulation is carried out using Simulink while Mod-elSim has been used to simulate the VHDL code (HDL co-simulation). Such simulation is mandatory in order to takeTable 1. FFT macroblock specifications.Implementation Pipelined Streaming I/ONumber of sample points 64Output ordering Natural orderScaling UnscaledRounding mode TruncationPhase factor bit width 8into account those blocks, which are only available as blackboxes.2.3. System-level tools at macroblock level methodologyThe STM methodology consists of modeling the FFT/IFFTmodule using the System Generator's FFT block (Table 1).In this methodology, it is only necessary to design an inter-face that adapts the input/output signals of the FFT block tothe module interface. In this case, the functional simulationis totally carried out using Simulink.3. DESIGN RESULTSIn this section, simulation and hardware implementation re-sults obtained for the three methodologies are described insome detail.3.1. Simulation resultsIn order to check that the designs work correctly, the fol-lowing simulation process has been carried out. At the first9DATA IN FFTAuthorized licensed use limited to: Universidad de Sevilla. Downloaded on January 11,2021 at 15:00:28 UTC from IEEE Xplore.  Restrictions apply. Table 2. Simulation results.VC STR STMClock cycles 291 291 262Mean error 1.0% 1.0% 2.1%stage, designs have been verified using Simulink and Mod-elSim. For the generation of the input stimuli, the SourceBlockset of Simulink has been employed. So, the input sig-nal (DATA INSFFT) has been generated with Matlab andexported to Simulink through the From-Workspace block.This input is conformed by 64 complex numbers where realand imaginary parts are values from -1 up to 1. At the sec-ond stage, once the simulation has been finished, the To-Workspace block has allowed us to compare the results withthe ones provided by the FFT Matlab function (the From/To-Workspace blocks provide an interface between Simulinkand Matlab). In order to estimate the results accuracy, theduration of the whole calculation as well as the relative er-ror of the output values have been measured (Table 2).As we can see, STM implementation consumes a loweramount of clock cycles for the calculation than VC and STR(from 291 to 262 cycles). However, both implementationsreduce the output error with respect to the STM one (from2.1% to 1.0%).3.2. Hardware implementation resultsIn order to compare the implementations of the differentFFT/IFFT designs, they have been synthesized separatelywith ISE, and implemented on a Virtex-II XC2V2000FPGA. This device has all the features necessary to im-plement DSP functions: two million system gates, 56embedded multipliers, and 56 Block RAMs.In Table 3, the implementation results for each designare shown. Two figures of merit are analyzed in this sec-tion: hardware resources used and maximum operation fre-quency. In terms of resource usage, the VC and STR im-plementations save about 4% slices with respect to STM de-sign. Analyzing the maximum operation frequency, we cansee that STM obtains the best result: 122 MHz as oppositeof 40 MHz.4. DISCUSSIONThe purpose of this section is to analyze the results obtainedand propose a specific methodology.Firstly, on the one hand, simulation results show that theSTM implementation reduces the amount of clock cyclesnecessary to the calculation from 291 to 262 cycles withrespect to VC and STR (Table 2). On the other hand, VCand STR reduce the output relative error from 2.1% to 1.0%with respect to STM. This is due to the internal data widththey employ: in the VC and STR implementations, design-ers fully control the internal structure and intermediate op-eration accuracy, whereas in the STM case, designers canonly configure the input signal accuracy, what increases theoutput error.Secondly, hardware implementation results show thatVC and STR obtain the best results in terms of resourceusage: they save about 4% slices with respect to STM(Table 3). This is because the system architecture designedis specifically suited for area optimization. In other way, wecan see that STM achieves the highest maximum operationfrequency: 122 MHz compared to 40 MHz of VC and STR.Moreover, if we consider that STM takes less clock cyclesto calculate the results, this implementation could be a goodalternative whether enough hardware resources are availableand results obtained are accurate enough.Comparing VC and STR, both designs produce simi-lar results, except for the use of embedded multipliers andBlock RAMs. Also, they reach an almost equal maximumoperation frequency of 40 MHz. This is because both de-signs implement the same architecture (Table 3).Thirdly, on the one hand, it is remarkable that usingsystem-level tools facilitates the design tasks greatly, allow-ing designers to focus on the system architecture and reduc-ing the design time in an important way. This is possible be-cause the library provided by the foundry is very optimizedfor the target programmable chips as well as the availableblocks are fully parametrizable: we can decide which onesuse on-chip resources (like BRAMs or embedded multipli-ers) or include different latency configurations (among otheravailable options). This fact allows designers to totally con-trol the way they are implemented and obtain a very effi-cient structure. On the other hand, System Generator doesnot count on some blocks that can be easily designed inVHDL, whose design becomes a tedious task by using aGUI (Graphical User Interface) tool, as for example registersets or decoders. Also, an important drawback is that someblocks can only be implemented on specific FPGA models.In terms of VHDL coding, we have to remark the greatamount of designs available through the Xilinx LogiCORErepository. This makes easier the design process althoughusing such language involves a difficult simulation processdue to the tediousness of the input stimuli generation. In thisway, we have employed an alternative: simulate the VHDLcode by HDL co-simulation.Finally, we have to conclude that STM is an interestingoption if the available macroblocks are suited to the specificaims: it offers good results in terms of resource usage andoperation frequency (but taking into account the possibledata width restriction); besides, it avoids having to designthe module, reducing the design time (Table 3). However,we have considered very important to maintain the controlover the internal structure (due to the precision aspect), so10Authorized licensed use limited to: Universidad de Sevilla. Downloaded on January 11,2021 at 15:00:28 UTC from IEEE Xplore.  Restrictions apply. Table 3. Hardware implementation results on Virtex-II XC2V2000.VC STR STMSlices 1187 (23%) 1188 (23%) 1393 (27%)Slice Flip Flops 624 (6%) 624 (6%) 2041 (19%)4 input LUTs 1984 (19%) 2030 (19%) 1380 (13%)Bonded IOBs 58 (33%) 58 (33%) 57 (33%)Block RAMs 2 (5%) 4 (10%) 3 (7%)MULT18x18 12 (30%) 4 (10%) 7 (17%)GCLKs 1 (6%) 1 (6%) 1 (6%)Maximum operation frequency 39.53 MHz 40.15 MHz 122.65 MHzDesign, testing, and on-chip verification time about 60 days j about 40 days Fabout 5 daysthat as a general methodology, our proposal combines bothVC and STR and it can be summarized as follows:1. Design the module with System Generator at RT levelbut using VHDL coding for those blocks that areeasier to program with such a language (these blockscan be included into the module through the BLACKBOX block).2. Verify the module by HDL co-simulation. This typeof verification employs Simulink to simulate the Sys-tem Generator blocks and ModelSim to simulate theVHDL ones (black boxes).Thus, the proposed methodology facilitates the designprocess greatly as well as it allows designers to maintainfull control over the module internal architecture and obtainan efficient structure.5. CONCLUSIONWe have compared three different methodologies for theFPGA implementation of a FFT/IFFT module: VHDLcoding, System-level tools at RT level, and System-leveltools at macroblock level. In terms of resource usage andmaximum operation frequency obtained, the last one hasoffered good results. However, such implementation has amain drawback: the internal data width cannot be controlledwhich yields to an important output error. Thus, as a generalmethodology, our proposal is to combine the two first ones(VC and STR) in order to count on the advantages of themboth: it facilitates the design process as well as allowsdesigners to maintain total control over the module internalarchitecture and obtain an efficient structure which greatlyreduces the output error.6. REFERENCES[1] L. Hanzo and T. Keller, OFDM and MC-CDMA: A Primer.Wiley-IEEE Press, 2006.[2] A. Millan, M. J. Bellido, J. Juan, P. Ruiz-de Clavijo, D. Guer-rero, and E. Ostua, "Disefio eficiente de un modulo FFT/IFFTsobre FPGA," in Proc. III Reconfigurable Computing and Ap-plications Conference (JCRA), Madrid (Spain), Sept. 2003, pp.107-114.[3] A. Millan, M. J. Bellido, J. Juan, P. Ruiz-de Clavijo, D. Guer-rero, E. Ostua, and J. Viejo, "Efficient design of a FFT/IFFT-64 module on ASIC," in Proc. XI Iberchip Workshop (IWS),Salvador de Bahia (Brazil), Mar. 2005, pp. 305-306.[4] P. J. Ashenden, The Designer's Guide to VHDL, 2nd ed. Aca-demic Press, 2002.[5] Xilinx System Generator for DSP v8.1 User's Guide, XilinxInc., 2005.[6] T. Widhe, J. Melander, and L. Wanhammar, "Design of ef-ficient radix-8 butterfly PEs for VLSI," in Proc. IEEE Inter-national Symposium on Circuits and Systems (ISCAS), vol. 3,Hong Kong (PRC), 1997, pp. 9-12.[7] J. M. Berge, A. Fonkoua, S. Maginot, and J. Rouillard, VHDLDesigner's Reference. Kluwer Academic Publishers, 1992.[8] J. Hwang, B. Milne, N.Shirazi, and J. Stroomer, "System LevelTools for DSP in FPGAs," in Proc. XI International Confer-ence on Field Programmable Logic and Applications (FPL),Belfast, Northern Ireland (UK), Aug 2001.11Authorized licensed use limited to: Universidad de Sevilla. Downloaded on January 11,2021 at 15:00:28 UTC from IEEE Xplore.  Restrictions apply. 

Implementation of a FFT/IFFT Module on FPGA: Comparison of Methodologies

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Implementation of a FFT/IFFT Module on FPGA: Comparison of Methodologies

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