In this paper we present a design of a peripheral for
MicroBlaze soft core processor as part of a R+D project
carried out in cooperation with three different companies.
The objective of the project consisted in the development of
an embedded system with a SoC implemented on a FPGA
custom-designed board. This work addresses the design of a
Digital Data Processing peripheral included as a part of the
target SoC application, that process digital signals via the
digital inputs on a proposed board. Peripheral functionality
is configurable for each digital signal independently and is
configured from the software running on the MicroBlaze
processor core.Ministerio de Educación y Cultura TEC2007-61802/MICJunta de Andalucía EXC-2005-TIC-102

Bellido Díaz, Manuel Jesús

Juan Chico, Jorge

Millán Calderón, Alejandro

Muñoz Rivera, Alejandro

Ostúa Arangüena, Enrique

Viejo Cortés, Julián

English

idUS. Depósito de Investigación Universidad de Sevilla

DIGITAL DATA PROCESSING PERIPHERAL DESIGN FOR AN EMBEDDEDAPPLICATION BASED ON THE MICROBLAZE SOFT COREE. Ostua, J Viejo, M.JBellido, A.Millan, J Juan & A.MunozGrupo de Investigacion y Desarrollo Digital (ID2)Departamento de Tecnologia Electronica - Universidad de SevillaAv. Reina Mercedes, s/n (E. T. S. Ingenieria Informatica) - 41012 Sevilla (Spain)Tel.: +34 954556160 - Fax: +34 954552764email: { ostua; julian; bellido; amillan; guerre; jjchico; paulino } @ dte.us.esABSTRACTIn this paper we present a design of a peripheral forMicroBlaze soft core processor as part of a R+D projectcarried out in cooperation with three different companies.The objective of the project consisted in the development ofan embedded system with a SoC implemented on a FPGAcustom-designed board. This work addresses the design of aDigital Data Processing peripheral included as a part of thetarget SoC application, that process digital signals via thedigital inputs on a proposed board. Peripheral functionalityis configurable for each digital signal independently and isconfigured from the software running on the MicroBlazeprocessor core.1. INTRODUCTIONThe continuous development of the integrated circuittechnology is leading to an increasing integration densitybesides an improvement of the operation speed ofelectronic systems. In digital systems, it allows for hugeperformance improvements while the system size shrinksmore and more. However, design methodologies are alsoincreasing in complexity, and new challenges are to befaced by designers. Two fundamental problems appear: onone hand, the increment in speed (switching activity) anddevice density translates in greater power consumption andpower and thermal density that may induce system failureunless effective cooling mechanisms are included; on theother hand, as integration density increases, the totalnumber of devices included in the chip increases (up toseveral million devices these days). Then, it becomesnecessary to define good design and verificationmethodologies in all the levels of abstraction in order tohandle effectively the complexity of the whole problem.One of the more extended methodologies in this sense isthe so-called System-on-Chip methodology or, moresimply, SoC design. The basic idea under this methodologyis to use the current integration possibilities not to designmore complex specific systems, like Intel or AMDprocessors, but to implement whole systems made out ofseveral individual building blocks on a single chip. Thisway, systems currently implemented out of several chips ona PCB (Printed Circuit Board) are being integrated in asingle chip while maintaining the overall structure of thesystem. This methodology provides many advantageswithout the need to completely re-define the way electronicdesigners work. Among these advantages are powerconsumption reduction, increased performance and muchmore miniaturization, making the SoC design a strongmethodology for embedded and ubiquitous applications.Almost 100% of the SoC's are digital systems builtaround a microprocessors that acts as a controlling unit. Theselected microprocessor will strongly condition theperformance and overall characteristics of the system, andthe cost of the SoC. It is important to note that mostembedded applications do not require high computationcapabilities, but usually demand high reliability and lowpower consumption.There are a several processor cores that are commonlyused in SoC applications, both privative cores that requiresthe acquisition of a license of use, like ARM [1], PowerPC[2], NIOS3 [3], MicroBlaze [4], and many others; and freeor open cores that may be used without the need to acquirea license, like LEON3 [5] and OpenRisc [6]. The mainadvantage of privative processors are that they are usuallywell tested and optimized for a specific target hardware andprovide a complete set of CAD tools to make the SoCdesign an easier process. For example, MicroBlaze fromXilinx is well integrated with the development platformfrom the same foundry, which leads to highly optimizeddesigns at the cost of being bound to a particular technology(Xilinx Spartan and Virtex FPGA families [7]) and aconcrete set of tools (Xilinx ISE and EDK [8]).This paper is the consequence of latest developments ofthe author's research team in the SoC design area. Adetailed view of the design and implementation of thedigital data processing function for industrial applications ispresented.978-1-4244-1992-0/08/$25.00 C2008 IEEE. 197Authorized licensed use limited to: Universidad de Sevilla. Downloaded on December 15,2020 at 18:24:58 UTC from IEEE Xplore.  Restrictions apply. Fig. 1. Digital Data Processing Peripheral functional diagramThe peripheral is part of the OpenRTU project, acompany effort to implement a System-on-Chip applicationleaded by a MicroBlaze processor core that will run on aSpartan-3 FPGA from Xilinx, on top of a custom-designedboard. The main functionality of the SoC system is thedigital signal (DSP) and digital data processing. That isaccomplished with two different peripherals implementedas IP cores on SoC and so embedded on the same FPGA asthe MicroBlaze. The digital data processing peripheral isthe object of this study.The rest of the paper is organized as follows: in the nextsection we provide a brief introduction to the peripheral bydiscussing the specifications. Section 3 describes the designand implementation methodology including the softwareand hardware design process and application integration.Section 4 presents the main results obtained in this project.Finally, some conclusions are derived in section 5.2. PERIPHERAL SPECIFICATIONSThe objective peripheral specifications are to process digitalsignals, acquired directly via digital inputs on the board,through a group of different functions. On Fig. 1 a diagramof the peripheral main components is shown, with a modulefor each processing function.Peripheral functionality is configurable for each digitalsignal independently in several parameters, which includesdisabling a signal passing through some of the processingfunctions, timing configuration on filters and memories,input signals grouping configuration, status registers on theinputs and others.Operation on the digital peripheral is configured fromthe software running on the MicroBlaze processor core.This goal is committed in the Peripheral Control box, wherea series of global configuration registers are available to beread and written with a pre-designed interface to the SoCOPB bus, where MicroBlaze communicates with others IPsin the design including this peripheral. There is also someconfigurable interrupt handling done in this core, in order tolet MicroBlaze know when a concrete process is completed.Also a polling of the information is possible from any OPBperipheral. The results of each instant process are doneavailable to the MicroBlaze processor who then capturesthe data, archives it in the RAM memory and finally thesoftware running process a large number of information.As described above, each of the digital inputs can passthrough several function modules in a chain, where adifferent task is committed on each signal independently oron grouped signals in each case.The first module in the chain is a digital inverter whereeach signal is configured to be inverted or not, dependingon the digital input work conditions to the DSP board.Then the signal is passed through the filter, where thedigital signal pulses with a width less than configurableparameter in milliseconds will be ignored.Next module is the changes memory, so after everychange in the signal, it will remain unaltered for aconfigurable period of time in milliseconds.The last signal processing module is the allocator, witha quite complex functionality. It first reorders the signalsaccording to the programmable configuration in order todescribe each signals real life functionality, so each digitalinput can be a single signal, a double signal (grouped withanother input), or a part of a group of signals in order tocollect misc digital data, like counters or numeric values.Next, each group of signals obtained is treated to identifythe nature of the values it concerns, again a configuredbehavior, activating some error flags if necessary andfinally the results are stored on the corresponding outputregisters. These tasks are accomplished together with thecounters, numeric value and results memory modules fromthe peripheral.198Authorized licensed use limited to: Universidad de Sevilla. Downloaded on December 15,2020 at 18:24:58 UTC from IEEE Xplore.  Restrictions apply. Core Peripheral Design MicroBlaze InterfaceFig. 2. SoC design methodologySo, in the counters module, each pulse on the input isused to increment a predefined counter associated to thatdigital signal.The numeric value module is used to convert aconfigurable group of inputs to a numeric value as theresulting 8-bit word, in one of the following output formats:2 BCD values, 1-of-8 word or regular binary.The results memory module goal is to store the mainresults of the processing modules so they can be availablein time when MicroBlaze requests them.3. PERIPHERAL DESIGN ANDIMPLEMENTATIONIn this section the more important concerns in the designand implementation of the peripheral are described indetail.After the analysis of the peripheral and complete projectspecifications, it was taken into consideration the designmethodology to be used and so what the flow of the designprocess will be. As the complexity of the design is not toohigh and the functionality is pretty well defined and dividedin several modules, the decision was to design the core ofthe peripheral in synthesizable VHDL, using the Xilinx ISEFoundation IDE tool in order to synthesize the model andimplement it to the target FPGA family. The simulator usedwas Modelsim, by Mentor. Also in order to design theinterface of the peripheral to MicroBlaze via the OPB Busthe tool Embedded Development Kit (EDK) by Xilinx wasused. Fig.2 illustrates the SoC design methodology used inthis project.Each functional module was written in VHDL,simulated and synthesized individually and then a latestmodule was designed to glue all the logic, includingconfiguration and output registers and also interconnect theperipheral as a slave of the OPB bus so it can communicatewith MicroBlaze.In order to model each functional module of theperipheral, each one was designed as a canonical finite statemachine written completely in VHDL. Once each blockends its processing it activates a signal that initiates the nextone in the chain. After the last step has finished main resultsare archived and are available to MicroBlaze, which canread them anytime before the next set of digital inputs areprocessed. Also it's possible to send an interrupt message tothe SoC interrupt controller when new results are available.All the elements in the peripheral work with a singleclock signal, at a maximum frequency of 90 NM4hz, as shownon the results chapter, a value over the specifications. Asthe timing specifications were not so restrictive and areaconsumption was important, also big effort was spent onarea optimization by reutilization of the complex functionsfor each signal and doing a serial processing when possible.The peripheral initialization is done in hardware with apulse of a single reset line and it can also be done insoftware by the program running on the MicroBlaze core.199Authorized licensed use limited to: Universidad de Sevilla. Downloaded on December 15,2020 at 18:24:58 UTC from IEEE Xplore.  Restrictions apply. Ioroc sioples5roc do les ~proc v ores Z pro..Z p st proc vali a valor fnal3 3 3 3 p ocs =IDa01 010 _44) 0000 ..L1D.( =0= 4310440 i j 0444 41 0 0 0 0 X _4 4_O00000 00.00... 0000 000000 J00000000 000000 0000001 1000000000000011 000000 0 io .00001 001000 000000 Z N 0001 1 =_eT__I_ _oo_o_oooooooioo 00000[Fig. 3. Simulation of the peripheral4. RESULTSMain simulation and implementation results are discussedin the chapter.Simulation was completed for each functional moduleindependently in the peripheral and later on the completecore. The interface to MicroBlaze was then added to thedesign and evaluated and synthesized with Xilinx EDKtool. It was finally included in the completed design for anon-chip verification, including others peripherals and IPcores developed for this SoC application. A screen captureof the simulation process on the complete peripheral isshown in Fig. 3.The synthesis and implementation of the peripheral wasdone with Xilinx ISE and ED}this process are shown in TablcTable 1. Implementation Iperipheral coreperipheral & microblazemax operational freq.5. CONCIT-n fhP tntPr uplhil[P t6. ACKNOWLEDGMENTSThis work has been partially supported by the Ministry ofEducation and Culture of the Spanish Government throughthe TEC2007-6 1802/MIC (HIPER) project and theAndalusian Regional Government's EXC-2005-TIC-1023project.7. REFERENCES[1] Steve Furber: "ARM system-on-chip architecture, 2ndedition", Ed. Addison-Wesley 2000.[2] "IBM PowerPC Quick Reference Guide", IBM Corp. 2005.(i toolkits and main results of [3] "NIOS 3.0 CPU Data Sheet", Altera Corporation, 2004,e1 for the target architecture. http:Hwww.altera.com/literature/ds/ds_nios_cpu.pdf[4] "Microblaze Processor Reference Guide", Xilinx Inc. 2005,Results for a Spartan-3 1500 http:Hwww.xilinx.com/ise/embedded/mb_ref guide.pdfslices total % [5] Jiri Gaisler, Sandi Habinc, Edvin Catovic: "GRLIB IP397 133 12 2 Library User's Manual", Gaisler Research, 2006,397 13312 2 http:Hwww.gaisler.com/products/grlib/grlib.pdf984 .....1332 ...792 Mhz [6] Damjan Lampret: "OpenRISC 1200 IP Core Specification",2001,http:Hwww. opencores. org/cvsget. cgi/or I k/or 1200/doc/orl200_spec.pdf[7] "Xilinx FPGA Silicon Devices", Xilinx Inc. 2006,LUSIONS http://xilinx.com/products/silicon_solutions/fpgas/[8] "Xilinx Logic Design and Embedded Design Tools", 2006,nrpcpAtptl flip AAcian nnrl http://xilinx.com/products/design resources/design toolHI LIIP1UPCpU WC IUlVUpPI-CSIILC LIIC dUCSIg1 UIIUimplementation of a digital data processing peripheral forMicroblaze as part of the SoC of a embedded system. Weused a methodology based on direct VHDL codification,including an interface to the microprocess core provided inpart by the partner tools, which results in a very goodperformance for the designed peripheral. Effectively,results shows that the design occupies less than 2% over a1500 Spartan-3 and the speed operation is higher than90Mhz.200Authorized licensed use limited to: Universidad de Sevilla. Downloaded on December 15,2020 at 18:24:58 UTC from IEEE Xplore.  Restrictions apply. 

Digital Data Processing Peripheral Design for an Embedded Application based on the Microblaze Soft Core

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Digital Data Processing Peripheral Design for an Embedded Application based on the Microblaze Soft Core

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idUS. Depósito de Investigación Universidad de Sevilla