Silicon carbide enabled medium voltage DC transmission systems for rapid electric vehicle charging in the UK

The expected proliferation of rapid EV chargers with more than 100 kW rating will place significant power demand on the UK distribution system. Due to the currently limited headroom in 11kV networks, reinforcement will be costly and disruptive. This paper proposes a medium voltage DC (MVDC) system that bypasses the 33kV/11kV and 11kV/400V AC transformers by transmitting 54 kV DC power directly to the EV charging stations. Additional benefits include the opportunity to reinforce integration of battery storage and photovoltaic sources as well as implement soft-open-points with an MVDC interconnection between asynchronous AC systems at lower voltages. The 33kV AC to 54 kV rectification in this system is proposed to be done by using a 29-level modular multilevel converter (MMC) implemented in 3.3 kV SiC MOSFETs. On the EV side, there will be a 54 kV to 800 V fully isolated DC/DC converter implemented with 3.3 kV SiC MOSFETs on the primary side and 1.2 kV SiC MOSFETs or Schottky diodes on the secondary side. This paper presents converter simulation results demonstrating improved performance in the MVDC system and shows this is only possible with SiC MOSFET technology as the losses using silicon IGBTs make the system less efficient compared to the existing system

Analysis of dynamic performance and robustness of silicon and SiC power electronics devices

The emergence of SiC power devices requires evaluation of benefits and issues of the technology in applications. This is important since SiC power devices are still not as mature as their silicon counterparts. This research, in its own capacity, highlights some of the major challenges and analyzes them through extensive experimental measurements which are performed in many different conditions seeking to emulate various applications scenarios. It is shown that fast SiC unipolar devices, inherently reduce the switching losses while maintain low conduction losses comparable with contemporary bipolar technologies. This translates into lower temperature excursions and an enhanced conversion efficiency. However, such high switching rates may trigger problems in the device utilizations. The switching rates influenced by the device input capacitance can cause significant ringing in the output, especially in SiC SBDs. Measurements show that switching rate of MOSFETs increases with increasing temperature in turn on and reduces in turn off. Hence, the peak voltage overshoot and oscillation severity of the SiC SBD increases with temperature during diode turn off. This temperature dependence reduces at the higher switching rates. So accurate analytical models are developed for predicting the switching energy in unipolar SiC SBDs and MOSFET pairs and bipolar silicon PiN and IGBT pairs. A key parameter for power devices is electrothermal robustness. SiC MOSFETs have already demonstrated such merits compared to silicon IGBTs, however not for MOSFET body diodes. This research has quantified this in comparison with the similarly rated contemporary device technologies like CoolMOS. In a power MOSFET, high switching rates coupled with the capacitance of drain and body causes a displacement current in the resistive path of P body, inducing a voltage on base of the parasitic NPN BJT which might forward bias it. This may lead to latch up and destruction if the thermal limits are surpassed. Hence, trade offs between switching energy and electrothermal robustness are explored for the silicon, SiC and superjunction power MOSFETs. Measurements show that performance of body diodes of SiC MOSFETs is the most efficient due to least reverse recovery. The minimum forward current for inducing dynamic latch up decreases with increasing voltage, switching rate and temperature for all technologies. The CoolMOS exhibited the largest latch up current followed by the SiC and silicon power MOSFETs. Another problem induced by high switching rates is the electrical coupling between complementing devices in the same phase leg which manifests as short circuits across the DC link voltage. This has been understood for silicon IGBTs with known corrective techniques, however it is seen that due to smaller Miller capacitance resulting from a smaller die area, the SiC module exhibits smaller shoot through currents in spite of higher switching rates and a lower threshold voltage. Measurements show that the shoot through current exhibits a positive temperature coefficient for both technologies the magnitude of which is higher for the silicon IGBT. The effectiveness of common techniques of mitigating shoot through is also evaluated, showing that solutions are less effective for SiC MOSFET because of the lower threshold voltages and smaller margins for a negative gate bias

Performance Instability of 650 V p-GaN Gate HEMTs under Temperature-Induced Negative Gate Bias Stresses

In this article, the effect of negative gate bias stress and temperature on threshold voltage (Vth) and on-state resistance (Ron) instability of 650 V Schottky p-GaN gate HEMT devices from different manufacturers was explored. It is found that the there was an immediate Vth drift once the device was stressed. With the decrease in the negative gate voltage (Vgs), the variation in Vth (∆Vth) and the variation in R on (∆Ron) became more significant. The measuring Vgs also played an important role when the testing Vgs was low. The low temperature can lead to the constant increment in ∆Vth , while ∆Vth decreased and then increased at elevated temperatures. The trapping/de-trapping speeds of electrons and holes were enhanced with temperature. The substantial increase in ∆Ron at high temperatures can increase the loss of devices to a great extent. The instability of the static performances of Schottky p-GaN gate HEMT devices are harmful to the real application

Performance Instability of 650 V p-GaN Gate HEMTs under Temperature-Induced Negative Gate Bias Stresses

In this article, the effect of negative gate bias stress and temperature on threshold voltage (Vth) and on-state resistance (Ron) instability of 650 V Schottky p-GaN gate HEMT devices from different manufacturers was explored. It is found that the there was an immediate Vth drift once the device was stressed. With the decrease in the negative gate voltage (Vgs), the variation in Vth (∆Vth) and the variation in R on (∆Ron) became more significant. The measuring Vgs also played an important role when the testing Vgs was low. The low temperature can lead to the constant increment in ∆Vth , while ∆Vth decreased and then increased at elevated temperatures. The trapping/de-trapping speeds of electrons and holes were enhanced with temperature. The substantial increase in ∆Ron at high temperatures can increase the loss of devices to a great extent. The instability of the static performances of Schottky p-GaN gate HEMT devices are harmful to the real application

Electrothermal Power Cycling to Failure of Discrete Planar, Symmetrical Double-Trench and Asymmetrical Trench SiC MOSFETs

While SiC MOSFETs are now being utilized in industry their robustness under heavy-duty applications still remains a concern. In this paper, the results of experimental measurements of degradation to failure of different structured SiC power MOSFETs, namely the planar, symmetrical double-trench and asymmetrical trench structures are presented following electrothermal stressing by power cycling to beyond the safe operating area (SOA) limits. The tests are categorised in to subsets with/without forced cooling. The first set of tests involve successive switchings of the devices under constant DC current supply while their case temperature is monitored in real-time to evaluate their thermal performance. The symmetrical double-trench and asymmetrical trench MOSFETs are found to experience a higher case temperature rise thus prone to breakdown while failure is not observed in the planar structured device. The second experiment stresses the devices during continuous power cyclings with force cooling applied, in which the symmetrical and asymmetrical double-trench MOSFETs still encounter failure with detectable breakdown on the gate oxides, compared with the planar device which only exhibits degradation, without failure, with indications of aging