Jahdi, Saeed

Yu, Renze

English

In practice, SiC MOSFET chips are often parallel-connected to promote the power rating. However, due to the potentially unequal circuit parameter and temperature distribution inside the power module, parallel devices suffer from different electrothermal stress, which may result in long-term reliability challenges. In this paper, the short circuit performance of parallel-connected Planar, Symmetrical and Asymmetrical Double-Trench SiC MOSFETs have been investigated. The impact of gate resistance and case temperature difference on current distribution of parallel SiC MOSFETs have been analyzed. The degradation pattern of key parameters of three types of devices have been studied

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                          Yu, R., & Jahdi, S. (2023). Degradation Pattern of ParallelSymmetrical and Asymmetrical Double-Trench SiC MOSFETs underRepetitive Short Circuits. In PCIM Europe 2023: InternationalExhibition and Conference for Power Electronics, Intelligent Motion,Renewable Energy and Energy Management (pp. 804-809). VDEVerlag. https://doi.org/10.30420/566091111Peer reviewed versionLink to published version (if available):10.30420/566091111Link to publication record in Explore Bristol ResearchPDF-documentThis is the accepted author manuscript (AAM). The final published version (version of record) is available onlinevia VDE at https://doi.org/10.30420/566091111. Please refer to any applicable terms of use of the publisher.University of Bristol - Explore Bristol ResearchGeneral rightsThis document is made available in accordance with publisher policies. Please cite only thepublished version using the reference above. Full terms of use are available:http://www.bristol.ac.uk/red/research-policy/pure/user-guides/ebr-terms/Degradation Pattern of Parallel Symmetrical and AsymmetricalDouble-Trench SiC MOSFETs under Repetitive Short CircuitsRenze Yu1, Saeed Jahdi1, Juefei Yang1, Phil Mellor1, Jose Ortiz Gonzalez2, Olayiwola Alatise21 Department of Electrical Engineering, University of Bristol, Bristol, UK2 School of Engineering, University of Warwick, Coventry, UKCorresponding author: Renze Yu, renze.yu@bristol.ac.ukSpeaker: Renze Yu, renze.yu@bristol.ac.ukAbstractIn practice, SiC MOSFET chips are often parallel-connected to promote the power rating. However,due to the potentially unequal circuit parameter and temperature distribution inside the power module,parallel devices suffer from different electrothermal stress, which may result in long-term reliabilitychallenges. In this paper, the short circuit performance of parallel-connected Planar, Symmetrical andAsymmetrical Double-Trench SiC MOSFETs have been investigated. The impact of gate resistance andcase temperature difference on current distribution of parallel SiC MOSFETs have been analyzed. Thedegradation pattern of key parameters of three types of devices have been studied.1 IntroductionWith advantages of wider bandgap, higher criticalelectric field and higher carrier mobility, SiliconCarbide (SiC) devices have faster switching speed,lower on-state resistance (Ron), higher breakdownfield and smaller chip area compared with Siliconcounterparts. These outstanding characteristicshave brought significant improvements to theindustry, greatly reducing the weight and cost of thepower electronics system. However, the reliabilityof SiC devices has been a constraint, especially inextreme conditions such as short circuits [1]–[4].Moreover, discrete SiC chip is unable to conducthigh current, so SiC chips are often parallelconnected to increase the power level. Theuneven parameter distribution among chips willeasily result in different current and temperaturedistribution among devices, and the inconsistentelectrical-thermal stress will cause chip degradationto varying degrees, which will ultimately lower theoverall reliability. In [5], the short circuit behavior ofWolfspeed 1.2 kV/300 A and Rohm 1.2 kV/180 Amulti-chip SiC module were compared. Test resultsfound out that the Cree module can only withstand3.2 µs while the Rohm module can suffer fromthe stress for 7 µs at 800 V. In [6], a half-bridgemodule was tested and it failed within 3 µs. Afterpost-failure investigation, both papers discoveredthat only some of the chips failed, and it wasinferred that the unequal parameter distribution wasthe root cause: the least reliable device determinedthe overall reliability of the module. In [7]–[9],the disparity of chip parameter was discussedand electrical-thermal models were developed toexplain the mechanism of short circuit currentdistribution. The spread of threshold voltage V thwas found to be the most responsible factor. In [10],the impact of parasitic inductance mismatches onshort circuit reliability was clarified. Suggestionswere given to the design of power module.Current studies mainly focus on reliability testing ofpower modules, or finding responsible parametersfor uneven current distribution. The evolutionpattern of parallel-connected SiC MOSFETs underdifferent electrical-thermal stress in the short circuitevent should be further investigated, which ishelpful to shed light on the device degradationmechanism and is crucial to the long-term reliabilityof SiC MOSFET devices. Thus, the short circuitreliability test rig for parallel SiC MOSFET devicesis established in this paper. The short circuit currentdistribution and the degradation of key parametersof parallel-connected Planar, Symmetricaland Asymmetrical trench SiC MOSFETs areinvestigated in different electrical-thermal stress.2 Experimental SetupThe short circuit schematic diagram and test boardfor parallel-connected SiC MOSFET devices areshown in Figure 1. The devices under test (DUTs)were Planar, Symmetrical, and Asymmetricaltrench MOSFETs. Each DUT had a separate gatedriver. Before the test, DUTs had been testedby source measuring unit (Keysight B2902A) tomake sure they have similar static parameters,and the difference would only be caused bythe external factors. The PCB board had beencarefully designed to ensure that two DUTs havesymmetrical current path and similar parasiticparameters. The synchronicity of the gate signalwas tested, and both gate drivers can give same+18/-5 V output simultaneously. Besides, shortcircuit currents were measured by Rogowski coil(CWT1), and the drain-source voltage (V ds) wasmeasured by the differential probe (GW-InstekGDP-100). All waveforms were captured usingthe oscilloscope (Keysight MSO7104 A 1-GHz 4GSa/s). The short circuit waveform and the staticperformance of parallel devices were characterizedevery 20 cycles.Fig. 1: Experimental set-up for short circuit test ofparallel devices, including the two devices undertest (DUTs) of the three SiC MOSFET structures,gate driver signal outputs, DC link capacitors andprobes.3 Effect of Rg mismatch3.1 Test results and analysisIn the test, all parameters were kept same andonly Rg was different. The test was carried out at400 V V ds and room temperature. The Rg of DUT 1(Planar SiC MOSFET 1, Symmetrical trench SiCMOSFET 1, Asymmetrical trench SiC MOSFET 1)and DUT 2 (Planar SiC MOSFET 2, Symmetricaltrench SiC MOSFET 2, Asymmetrical trench SiCMOSFET 2) was 11 Ω and 22 Ω, respectively. Theshort circuit duration (tsc) was 10 µs, and testperiod was 10 s. Key static parameters of deviceshave been listed in Table 1. For all types of devices,the variations of V th and on-state resistance (Ron)are both below 2%. In this way, the differencebetween devices can be ignored and the onlyvariable was Rg.V th (V) Ron (mΩ)Planar 1 3.34 145.11Planar 2 3.34 144.42Variance 0% 0.48%Symmetrical Trench 1 4.42 133.96Symmetrical Trench 2 4.44 133.30Variance 0.45% 0.49%Asymmetrical Trench 1 4.74 105.25Asymmetrical Trench 2 4.74 103.68Variance 0% 1.51%Tab. 1: Key parameters of parallel devices under shortcircuit test with different Rg.The short circuit current distribution of threetypes of devices after the first cycle are shownin Figure 2. It can be discovered that the deviceswith higher Rg has lower peak current, but thedifference is negligible in the current droppingphase. The 11 Ω difference in Rg seems to haveno impact on the short circuit current distributionbetween planar devices, which is because of itslarge input capacitance that reduces the switchingspeed. Compared with Symmetrical trench devices,Asymmetrical trench devices are more sensitive toRg difference due to smaller input capacitance andfaster switching speed.3.2 Degradation of key parameters3.2.1 Degradation of V thThe degradation of V th of three types paralleldevices are shown in Figure 3. The Planardevices almost exhibit no degradation after 100Fig. 2: Impact of Rg difference on short circuit currentdistribution.Fig. 3: Degradation of V th under short circuit test withdifferent Rg.cycles, and V th remains stable around 3.2-3.3 V.For Symmetrical trench devices, V th graduallyreduces before 80 cycles with similar extent,which is the result of positive charge injection intothe gate oxide under the negative turn-off V gsstress [11], [12]. At the 100th cycle, V th increasesfor both parallel-connected devices, indicating thedegradation mode of the gate oxide has beendifferent. With regard to Asymmetrical trenchdevices, V th of both DUTs continuously reducesthroughout the test, but the device with lowerRg degrades faster. This makes sense becauseaccording to Figure 2, the device with lower Rg hashigher current, thereby having higher short circuitenergy and higher junction temperature, whichincreases the possibility for holes to overcome theSiC/SiO2 barrier and causes more significant V thdrift [13].3.2.2 Degradation of RonThe degradation of Ron of three types ofparallel-connected devices are demonstratedin Figure 4. It can be discovered that Ron of Planarand Asymmetrical devices remains rather stableand almost shows no degradation, which indicatesthat the bond wires and the top Al layer of the chipFig. 4: Degradation of Ron under short circuit test withdifferent Rg.Fig. 5: Degradation of Igss under short circuit test withdifferent Rg.are still in healthy state [14]. The degradation ofV th has minor impact on Ron measured at highV gs. For Symmetrical trench device with higherRg, Ron could not be measured at the last cycleanymore because its gate has been damaged andthe test condition has gone beyond the limit ofsource measuring unit.3.2.3 Degradation of IgssIgss is a indicator of gate oxide healthiness. TheIgss degradation of DUTs are depicted in Figure 5.Based on the test results, the gate oxides for bothPlanar devices are healthy and show no indicationof degradation after 100 cycles. For Symmetricaland Asymmetrical trench devices, Igss degradesfaster for devices with lower Rg. The reasonbehind is because the current switches faster andis larger when lower Rg is applied. With sameV ds, devices with lower Rg suffer from higher shortcircuit energy and their gate oxides undergo higherelectrical-thermal-mechanical stress.3.2.4 Degradation of EscTo analyze the degradation of chip parameterson short circuit performance of parallel-connectedFig. 6: Degradation of Esc under short circuit test withdifferent Rg.devices, short circuit energy (Esc) has beencalculated and plotted in Figure 6. It could bediscovered that the devices with smaller Rg alwayshave larger Esc compared with the devices withlarger Rg. For Planar devices, since no parametersdegrade significantly, Esc for both devices remainsroughly unchanged. For Symmetrical trenchdevices, Esc drops at the end of test cycle dueto the large Igss, which reduces the V gs and shortcircuit current. As for Asymmetrical trench devices,Esc slightly increases for both devices, and thedevice with lower Rg has greater increase. This isbecause the reduced V th speeds up the turn-on ofdevices.4 Effect of T case mismatch4.1 Test results and analysisTo investigate the effect of case temperature(T case) mismatch on current distribution, DUT 3(Planar SiC MOSFET 3, Symmetrical trench SiCMOSFET 3, Asymmetrical trench SiC MOSFET 3)was kept at 25 ◦C, and DUT 4 (Planar SiCMOSFET 4, Symmetrical trench SiC MOSFET 4,Asymmetrical trench SiC MOSFET 4) was attachedto a heating block to heat up the device to 125 ◦C.The test was carried out at V ds of 400 V & Rg of22 Ω. The tsc and test period were 10 µs and 10 s,respectively. Key static parameters of devices havebeen listed in Table 2. Similarly, the variations ofV th and Ron for all types of devices are both below2%. The only variable in the test is T case.According to the results in Figure 7, it could bediscovered that the higher the temperature, thefaster the devices switch, but the lower peak currentwill be. The underlying reason is due to the negativetemperature coefficient of V th and carrier mobility.With higher temperature, V th and lower mobility areV th (V) Ron (mΩ)Planar 3 3.30 142.87Planar 4 3.26 144.60Variance 1.23% 1.21%Symmetrical Trench 3 4.56 142.96Symmetrical Trench 4 4.55 139.47Variance 0.21% 1.79%Asymmetrical Trench 3 4.70 111.08Asymmetrical Trench 4 4.74 111.04Variance 0.85% 0.04%Tab. 2: Key parameters of parallel devices under shortcircuit test with different temperature.Fig. 7: Impact of T case difference on short circuit currentdistribution.reduced, resulting in the asynchronous turn-on anduneven current distribution, which is particularlyobvious for Planar devices.4.2 Degradation of key parameters4.2.1 Degradation of V thThe degradation of V th of DUTs are illustratedin Figure 8. The V th of both planar devices does notpresent any sign of degradation after 100 cyclesof short circuit stress, albeit slight fluctuation. ForSymmetrical trench devices, the device with higherT case ultimately has more V th degradation, whichdecreases from 4.58 V to 4.42 V. With respect toAsymmetrical trench devices, a more significantdegradation has also occurred to the device withhigher T case, whose V th reduces from 4.71 Vto 3.58 V within 100 cycles, while V th for thedevice tested at room temperature only drops from4.72 V to 4.29 V. It seems that for Symmetrical andAsymmetrical trench devices, although the highershort circuit current is higher for devices with lowerT case, the initial high T case has more impact on thedevice degradation.Fig. 8: Degradation of V th under short circuit test withdifferent T case.Fig. 9: Degradation of Ron under short circuit test withdifferent T case.4.2.2 Degradation of RonThe degradation of Ron of DUTs with differentT case are illustrated in Figure 9. For three typesof devices, the effect of uneven T case distributionwill not cause obvious Ron degradation betweenparallel-connected devices after 100 cycles ofshort circuit impulses. The drift region, chipsurface and packaging of Planar, Symmetrical andAsymmetrical trench devices are still intact.4.2.3 Degradation of IgssThe degradation of Igss after 100 short circuit cyclesare shown in Figure 10. According to the testresults, the Symmetrical trench device with lowerT case has the lowest gate oxide reliability. Althoughits Igss is still low, the sudden increase of Igssafter 80 cycles indicates irreversible damages hasalready arisen inside. As for the rest of devices, Igssremains at nA level, suggesting their gate oxidesare still healthy.4.2.4 Degradation of EscTo investigate the degradation of static parameterson the short circuit behaviour of parallel-connecteddevices under different T case, Esc under differentFig. 10: Degradation of Igss under short circuit test withdifferent T case.Fig. 11: Degradation of Esc under short circuit test withdifferent T case.test cycles has been computed and demonstratedin Figure 11. Interestingly, Esc is smaller forplanar device with lower T case while it is smallerfor Symmetrical and Asymmetrical trench deviceswith higher T case. In addition, Esc is quite steadyfor Planar and Symmetrical trench devices. Forboth Asymmetrical trench devices, Esc increases,and the device with higher temperature has largervariation because larger V th reduction.5 ConclusionIn this paper, the impact of Rg and T case differenceon short circuit current distribution and devicedegradation of parallel-connected SiC MOSFETsis discussed. Results indicate that parallelAsymmetrical trench devices are sensitive touneven Rg because of its fast switching speed,while the Planar and Symmetrical trench SiCMOSFETs are less affected by Rg differences. Inaddition, the devices with lower Rg degrade fasterbecause of higher electrical-thermal stress causedby larger short circuit current and higher Esc. Theuneven distribution of T case has a significant effecton current distribution for all types of devices.Based on test results, Planar devices almost exhibitno degradation after 100 cycles of short circuit test,and the device with higher T case has larger Esc.However, Symmetrical and Asymmetrical trenchdevices with higher T case degrade faster and havelower Esc.References[1] J. Yang, S. Jahdi, B. Stark, O. Alatise, J.Ortiz-Gonzalez, and P. Mellor, “Analysis of the 1stand 3rd quadrant transients of symmetrical andasymmetrical double-trench sic power mosfets,”IEEE Open Journal of Power Electronics, vol. 2,pp. 265–276, 2021. DOI: 10.1109/OJPEL.2021.3072503.[2] R. Yu, S. Jahdi, P. Mellor, J. Yang, C. Shen,et al., “Investigation of repetitive short circuitstress as a degradation metric in symmetrical andasymmetrical double-trench sic power mosfets,” inIEEE Workshop on Wide Bandgap Power Devicesand Applications in Europe (WiPDA Europe), Sep.2022, pp. 1–6. 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Degradation Pattern of Parallel Symmetrical and Asymmetrical Double-Trench SiC MOSFETs under Repetitive Short Circuits

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Degradation Pattern of Parallel Symmetrical and Asymmetrical Double-Trench SiC MOSFETs under Repetitive Short Circuits

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