The LCLS-II Gun & Buncher LLRF Controller Upgrade

LCLS-II is currently in its commissioning phase at SLAC. It is an X-ray FEL driven by a CW superconducting LINAC. The beam injector plays a crucial role in the overall performance of the accelerator, and is critical to the final electron beam performance parameters. The LCLS-II injector comprises of a 185.7 MHz VHF copper gun cavity, and a 1.3 GHz two-cell L-band copper buncher cavity. The FPGA-based controller employs feedback and Self-Excited Loop logic in order to regulate the cavity fields. It also features several other functionalities, such as live detune computation, active frequency tracking, and waveform recording. The LLRF system drives the cavities via two 60 kW SSAs through two power couplers, and thus stabilizes the fields inside the plant. This paper provides an outline of the general functionalities of the system, alongside a description of its hardware, firmware and software architecture, before finalizing with the current status of the project and its future goals.Comment: Poster presented at LLRF Workshop 2022 (LLRF2022, arXiv:2208.13680

Modelling Processes and Products in the Cereal Chain

[EN] In recent years, modelling techniques have become more frequently adopted in the field of food processing, especially for cereal-based products, which are among the most consumed foods in the world. Predictive models and simulations make it possible to explore new approaches and optimize proceedings, potentially helping companies reduce costs and limit carbon emissions. Nevertheless, as the different phases of the food processing chain are highly specialized, advances in modelling are often unknown outside of a single domain, and models rarely take into account more than one step. This paper introduces the first high-level overview of modelling techniques employed in different parts of the cereal supply chain, from farming to storage, from drying to milling, from processing to consumption. This review, issued from a networking project including researchers from over 30 different countries, aims at presenting the current state of the art in each domain, showing common trends and synergies, to finally suggest promising future venues for research.The authors would like to acknowledge networking and article processing charge support by COST Action CA15118 (Mathematical and Computer Science Methods for Food Science and Industry).Carvalho, O.; Charalambides, MN.; Djekic, I.; Athanassiou, C.; Bakalis, S.; Benedito Fort, JJ.; Briffaz, A.... (2021). Modelling Processes and Products in the Cereal Chain. Foods. 10(1):1-18. https://doi.org/10.3390/foods10010082S11810

Modelling Processes and Products in the Cereal Chain

ReviewIn recent years, modelling techniques have become more frequently adopted in the field of food processing, especially for cereal-based products, which are among the most consumed foods in the world. Predictive models and simulations make it possible to explore new approaches and optimize proceedings, potentially helping companies reduce costs and limit carbon emissions. Nevertheless, as the different phases of the food processing chain are highly specialized, advances in modelling are often unknown outside of a single domain, and models rarely take into account more than one step. This paper introduces the first high-level overview of modelling techniques employed in different parts of the cereal supply chain, from farming to storage, from drying to milling, from processing to consumption. This review, issued from a networking project including researchers from over 30 different countries, aims at presenting the current state of the art in each domain, showing common trends and synergies, to finally suggest promising future venues for researchinfo:eu-repo/semantics/publishedVersio

SCA eXtension: a Design for FPGA Parameter Configuration within the ATLAS DAQ Scheme

The foreseen upgrades of the Large Hadron Collider (LHC) are expected to increase the demand in throughput of the front-end and back-end electronics that support the readout of the LHC detectors. Therefore, the complexity of the electronics systems will be increased as well. An example of this, is the electronics system of the New Small Wheel (NSW) upgrade of the Toroidal LHC ApparatuS (ATLAS) detector, which will be comprised of a plethora of Field-Programmable Gate Arrays (FPGAs) and Application-Specific Integrated Circuits (ASICs). The Slow Control Adapter eXtension (SCAX), is an FPGA module, designed to support FPGA systems that are part of the ATLAS electronics scheme by writing into and reading back the configuration parameters of their logic. This work describes the context of the SCAX's implementation, as well as architectural considerations of the module and techniques to validate its hardware implementation

SCA eXtension: a Design for FPGA Parameter Configuration within the ATLAS DAQ Scheme

The foreseen upgrades of the Large Hadron Collider (LHC) are expected to increase the demand in throughput of the front-end and back-end electronics that support the readout of the LHC detectors. Therefore, the complexity of the electronics systems will be increased as well. An example of this, is the electronics system of the New Small Wheel (NSW) upgrade of the Toroidal LHC ApparatuS (ATLAS) detector, which will be comprised of a plethora of Field-Programmable Gate Arrays (FPGAs) and Application-Specific Integrated Circuits (ASICs). The Slow Control adapter eXtension (SCAX), has been designed to support FPGA systems that are part of the ATLAS electronics scheme. This work describes the context of the SCAX's implementation, as well as architectural considerations of the module and techniques to validate its hardware implementation

Front-End and Back-End Electronics for the ATLAS New Small Wheel Upgrade

The upgrades of the Large Hadron Collider (LHC) at CERN and the experiments in 2019/20 and 2024/26 will allow to increase the instantaneous luminosity. During LS2, each of the so-called "Small Wheels" of the ATLAS muon spectrometer are planned to be replaced by the "New Small Wheel" (NSW), which will be comprised of two gaseous detector technologies, namely the Micromegas (MM), mainly used for track reconstruction and the small strip Thin Gap Chambers (sTGC), mainly used for triggering. The 2.4 million readout channels of those chambers will require a new generation of electronics to read them out, that will be able to endure a harsh radiation environment while at the same time be compatible with the Phase-II trigger rates, which are expected to reach a Level-0 frequency of 1 MHz and a Level-1 frequency of 400 kHz. Several custom Application-Specific-Integrated-Circuits (ASICs) have been developed for the electronics system of the NSW, besides special boards to house these ASICs, as well as dedicated Field-Programmable Gate Array (FPGA) designs. A general overview of the main elements of the NSW electronics scheme is provided here

VMM3a: an ASIC for Tracking Detectors

The VMM3a is a custom Application Specific Integrated Circuit (ASIC). It will be used as the front ASIC for both Micromegas and sTGC detectors of the ATLAS Muon New Small Wheels upgrade at CERN. Due to its highly configurable parameters, it has been proposed a variety of tracking detectors and another experiments. It is fabricated in the 130nm Global Foundries 8RF-DM process. The ASIC integrates 64 independently configurable channels each providing amplitude and timing measurements, in digital or analog format. The design aspects and performance of the VMM3a as a production ASIC will be presented

Research and Development of the Electronics and Data Acquisition System for the New Small Wheel Upgrade of the ATLAS Detector at CERN and Performance Evaluation of the Micromegas Chamber

The Large Hadron Collider (LHC) at CERN, which began operations in 2008, has allowed the scientific community to conduct groundbreaking experiments that aim to answer fundamental questions about energy and matter. Since the high energy physics experiments rely heavily on statistics, the increase of reaction rate is considered to be of utmost importance. The higher the reaction rate, the more data are recorded, and rare events that would otherwise be hidden by other processes, emerge. For this reason, the LHC plans to perform upgrades in the way it delivers its beams, leading to a higher center-of-mass energy and instantaneous luminosity. After the second Long Shutdown (LS2) upgrade, which will be finalized in 2021, the beams will have an ultimate luminosity of \mathscr{L} = 2.5 \times 10^{34}\, \m{cm^{-2}s^{-1}}. Additional upgrades that will lead to the so-called Phase-II (2026-2038), will see the LHC deliver a luminosity of 5-7.5 \times 10^{34}\, \m{cm^{-2}s^{-1}} and a center-of-mass energy of 14\, \m{TeV}. The increase in luminosity will lead to an increase in reaction rate and hence, particle flux, stressing the LHC's detectors and their associated data acquisition systems to their limits. For this reason, the Toroidal LHC ApparatuS (ATLAS) detector, the largest of the LHC, is planned to replace its innermost end-cap stations of its muon spectrometer during LS2. The New Small Wheel (NSW) upgrade as it is called, will be comprised of two detector technologies, the Micromegas (MM) and the small-strip Thin Gap Chambers (sTGC). Designed to cope with the increased background rate of future run conditions, the NSW will provide muon precision tracking data to ATLAS, and also contribute to its triggering scheme. In order to support the newly-installed detector media, a next-generation data acquisition system was designed, that will be able to cope with the increasing demand in throughput in the following years of ATLAS' operation, and endure the harsh radiation environment of the innermost end-cap region of the muon spectrometer. The cornerstone of the said front-end electronics system, is the VMM Application-Specific Integrated Circuit (ASIC), which will be used as the front-end chip for both Micromegas and sTGC detectors of the ATLAS NSW upgrade. Due to its flexibility and several configurable parameters, it has also been proposed to a variety of tracking detectors in other experiments. The VMM integrates 64 independent channels, each providing precise amplitude and timing measurements in digital format for tracking purposes, and fast signals for triggering. This mixed-signal all-in-one solution, underwent three major revisions and a minor one, since its first prototype that was produced in 2012. None of these revisions could had been conducted, if a reliable testing and characterization platform did not exist. This gap was filled by the VMM Readout System (VRS), which employs Field-Programmable Gate Array (FPGA) devices that reside on the same board that the VMM is on. This FPGA is able to configure, read-out and calibrate the ASIC, and be adaptable to different implementation scenarios (i.e. testbench and testbeam use-cases), and different boards or FPGA packages. A large part of this dissertation, is devoted into describing this FPGA firmware that was developed for the needs of the NSW upgrade. The firmware was employed to validate the ASIC's performance, perform the mass-testing of its final production version, and handle the tracking and triggering data when the VMM was used in conjunction with the early Micromegas chamber prototypes during testbeam, thus aiding the collaboration in determining the operational parameters of the detector and its front-end ASIC. After the production of the final ASICs that would read-out and configure the VMM, the FPGA readout scheme was replaced by the final one, which made use of the next-generation data acquisition scheme of ATLAS, the Front-End LInk eXchange (FELIX). Another significant part of this work, describes the integration process of the NSW electronics system with FELIX and its related back-end infrastructure, which involved the development of software tools that eased the integration process, and the Micromegas detector commissioning prior to its deployment into the ATLAS cavern. Finally, the last Chapter of this dissertation, is devoted into describing the Slow Control Adapter eXtension (SCAX), which is an FPGA module that emulates the SCA ASIC. The latter is a radiation-tolerant device housed by all front-end boards of the NSW electronics system, and is used to access the register address space of other ASICs, in order to configure and monitor them. The SCAX on the other hand, is designed to support FPGA systems that are part of the ATLAS electronics scheme and are situated outside the radiation area, by writing into the configuration parameters or reading back any of the status registers of their logic. The SCAX emulates both the I2C interface of the SCA ASIC used by the NSW devices, as well as the communication protocol implemented between itself and the back-end electronics scheme. It thereby enables using the same back-end software suite that support the ASICs, to also access the address space of the FPGAs within the same system. It is being used by the NSW Trigger Processor, and can be employed by any FPGA that interfaces with FELIX

SCA eXtension: a Design for FPGA Parameter Configuration within the ATLAS DAQ Scheme

The foreseen upgrades of the Large Hadron Collider (LHC) are expected to increase the demand in throughput of the front-end and back-end electronics that support the readout of the LHC detectors. Therefore, the complexity of the electronics systems will be increased as well. An example of this is the electronics system of the New Small Wheel (NSW) upgrade of the Toroidal LHC ApparatuS (ATLAS) detector, which will be comprised of a plethora of Field-Programmable Gate Arrays (FPGAs), and Application-Specific Integrated Circuits (ASICs). These ASICs will be configured and monitored by the Slow Control Adapter (SCA), another ASIC designed for this purpose. The Slow Control Adapter eXtension (SCAX) on the other hand, is an FPGA module designed to support FPGA systems that are part of the ATLAS electronics scheme by writing into the configuration parameters or reading back any of the status registers of their logic. SCAX emulates both the I2C interface of the SCA used by the NSW ASICs, as well as the communication protocol implemented between the SCA and the back-end infrastructure. It thereby enables using the same OPC-UA server and back-end software suite that support the ASICs, to also interface with the FPGAs that are part of the same system. This work describes the context of the SCAX's implementation, alongside architectural considerations of the module, features, and techniques to validate its hardware implementation