SCA eXtension: a Design for FPGA Parameter Configuration within the ATLAS DAQ Scheme

Abstract

The foreseen upgrades of the Large Hadron Collider (LHC) are expected to increase the demand in throughput of the front-end and back-end electronics that support the readout of the LHC detectors. Therefore, the complexity of the electronics systems will be increased as well. An example of this, is the electronics system of the New Small Wheel (NSW) upgrade of the Toroidal LHC ApparatuS (ATLAS) detector, which will be comprised of a plethora of Field-Programmable Gate Arrays (FPGAs) and Application-Specific Integrated Circuits (ASICs). The Slow Control adapter eXtension (SCAX), has been designed to support FPGA systems that are part of the ATLAS electronics scheme. This work describes the context of the SCAX's implementation, as well as architectural considerations of the module and techniques to validate its hardware implementation