SCA eXtension: a Design for FPGA Parameter Configuration within the ATLAS DAQ Scheme

Abstract

The foreseen upgrades of the Large Hadron Collider (LHC) are expected to increase the demand in throughput of the front-end and back-end electronics that support the readout of the LHC detectors. Therefore, the complexity of the electronics systems will be increased as well. An example of this is the electronics system of the New Small Wheel (NSW) upgrade of the Toroidal LHC ApparatuS (ATLAS) detector, which will be comprised of a plethora of Field-Programmable Gate Arrays (FPGAs), and Application-Specific Integrated Circuits (ASICs). These ASICs will be configured and monitored by the Slow Control Adapter (SCA), another ASIC designed for this purpose. The Slow Control Adapter eXtension (SCAX) on the other hand, is an FPGA module designed to support FPGA systems that are part of the ATLAS electronics scheme by writing into the configuration parameters or reading back any of the status registers of their logic. SCAX emulates both the I2C interface of the SCA used by the NSW ASICs, as well as the communication protocol implemented between the SCA and the back-end infrastructure. It thereby enables using the same OPC-UA server and back-end software suite that support the ASICs, to also interface with the FPGAs that are part of the same system. This work describes the context of the SCAX's implementation, alongside architectural considerations of the module, features, and techniques to validate its hardware implementation