Research and Development of the Electronics and Data Acquisition System for the New Small Wheel Upgrade of the ATLAS Detector at CERN and Performance Evaluation of the Micromegas Chamber

Abstract

The Large Hadron Collider (LHC) at CERN, which began operations in 2008, has allowed the scientific community to conduct groundbreaking experiments that aim to answer fundamental questions about energy and matter. Since the high energy physics experiments rely heavily on statistics, the increase of reaction rate is considered to be of utmost importance. The higher the reaction rate, the more data are recorded, and rare events that would otherwise be hidden by other processes, emerge. For this reason, the LHC plans to perform upgrades in the way it delivers its beams, leading to a higher center-of-mass energy and instantaneous luminosity. After the second Long Shutdown (LS2) upgrade, which will be finalized in 2021, the beams will have an ultimate luminosity of \mathscr{L} = 2.5 \times 10^{34}\, \m{cm^{-2}s^{-1}}. Additional upgrades that will lead to the so-called Phase-II (2026-2038), will see the LHC deliver a luminosity of 5-7.5 \times 10^{34}\, \m{cm^{-2}s^{-1}} and a center-of-mass energy of 14\, \m{TeV}. The increase in luminosity will lead to an increase in reaction rate and hence, particle flux, stressing the LHC's detectors and their associated data acquisition systems to their limits. For this reason, the Toroidal LHC ApparatuS (ATLAS) detector, the largest of the LHC, is planned to replace its innermost end-cap stations of its muon spectrometer during LS2. The New Small Wheel (NSW) upgrade as it is called, will be comprised of two detector technologies, the Micromegas (MM) and the small-strip Thin Gap Chambers (sTGC). Designed to cope with the increased background rate of future run conditions, the NSW will provide muon precision tracking data to ATLAS, and also contribute to its triggering scheme. In order to support the newly-installed detector media, a next-generation data acquisition system was designed, that will be able to cope with the increasing demand in throughput in the following years of ATLAS' operation, and endure the harsh radiation environment of the innermost end-cap region of the muon spectrometer. The cornerstone of the said front-end electronics system, is the VMM Application-Specific Integrated Circuit (ASIC), which will be used as the front-end chip for both Micromegas and sTGC detectors of the ATLAS NSW upgrade. Due to its flexibility and several configurable parameters, it has also been proposed to a variety of tracking detectors in other experiments. The VMM integrates 64 independent channels, each providing precise amplitude and timing measurements in digital format for tracking purposes, and fast signals for triggering. This mixed-signal all-in-one solution, underwent three major revisions and a minor one, since its first prototype that was produced in 2012. None of these revisions could had been conducted, if a reliable testing and characterization platform did not exist. This gap was filled by the VMM Readout System (VRS), which employs Field-Programmable Gate Array (FPGA) devices that reside on the same board that the VMM is on. This FPGA is able to configure, read-out and calibrate the ASIC, and be adaptable to different implementation scenarios (i.e. testbench and testbeam use-cases), and different boards or FPGA packages. A large part of this dissertation, is devoted into describing this FPGA firmware that was developed for the needs of the NSW upgrade. The firmware was employed to validate the ASIC's performance, perform the mass-testing of its final production version, and handle the tracking and triggering data when the VMM was used in conjunction with the early Micromegas chamber prototypes during testbeam, thus aiding the collaboration in determining the operational parameters of the detector and its front-end ASIC. After the production of the final ASICs that would read-out and configure the VMM, the FPGA readout scheme was replaced by the final one, which made use of the next-generation data acquisition scheme of ATLAS, the Front-End LInk eXchange (FELIX). Another significant part of this work, describes the integration process of the NSW electronics system with FELIX and its related back-end infrastructure, which involved the development of software tools that eased the integration process, and the Micromegas detector commissioning prior to its deployment into the ATLAS cavern. Finally, the last Chapter of this dissertation, is devoted into describing the Slow Control Adapter eXtension (SCAX), which is an FPGA module that emulates the SCA ASIC. The latter is a radiation-tolerant device housed by all front-end boards of the NSW electronics system, and is used to access the register address space of other ASICs, in order to configure and monitor them. The SCAX on the other hand, is designed to support FPGA systems that are part of the ATLAS electronics scheme and are situated outside the radiation area, by writing into the configuration parameters or reading back any of the status registers of their logic. The SCAX emulates both the I2C interface of the SCA ASIC used by the NSW devices, as well as the communication protocol implemented between itself and the back-end electronics scheme. It thereby enables using the same back-end software suite that support the ASICs, to also access the address space of the FPGAs within the same system. It is being used by the NSW Trigger Processor, and can be employed by any FPGA that interfaces with FELIX