Energy efficient design of flexible truncated multipliers.

Multipliers are present in almost all Digital Signal Processing systems. They are area and power demanding structures that constrain the timing and resolution parameters of the entire DSP unit, making the implementation of e cient parallel multipliers desirable to achieve low-power arithmetic systems. Truncated multiplication reduces the power required by multipliers by only computing the most-signi cant bits of the product. The most common approach to truncation includes physical reduction of the partial product matrix and a compensation for the reduced bits via di erent hardware compensation subcircuits. However, this results in fixed systems optimized for a given application at design time. A novel approach to truncation is proposed, where a full precision multiplier is implemented, but the active section of the partial product matrix is selected dynamically at run-time. This allows a power reduction tradeoff against signal degradation which can be modified at any time. Such an architecture brings together the power reduction bene ts from truncated multipliers and the flexibility of reconfigurable and general purpose devices. Effective implementation of such a multiplier is presented in a custom dig- ital signal processor, where the concepts of software compensation and multi-level truncation are introduced and analyzed for different applications. Experimental results are studied, including power measurements from both post-synthesis simulations and a fabricated IC implementation, featuring the rst system-level DSP core using a ne-grain programmable truncated multiplier. Fault-tolerant techniques are also studied from an energy e ciency point of view. The application of such techniques to the proposed DSP architecture shows that, not only energy reductions from both truncated multiplication and fault tolerance can coexist, but the existence of synergies between both techniques to obtain lower energy consumption for DSP architecture