8 research outputs found

    On the robustness of ultra-high voltage 4H-SiC IGBTs with an optimized retrograde p-well

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    The robustness of ultra-high voltage (>10kV) SiC IGBTs comprising of an optimized retrograde p-well is investigated. Under extensive TCAD simulations, we show that in addition to offering a robust control on threshold voltage and eliminating punch-through, the retrograde is highly effective in terms of reducing the stress on the gate oxide of ultra-high voltage SiC IGBTs. We show that a 10 kV SiC IGBT comprising of the retrograde p-well exhibits a much-reduced peak electric field in the gate oxide when compared with the counterpart comprising of a conventional p-well. Using an optimized retrograde p-well with depth as shallow as 1 μm, the peak electric field in the gate oxide of a 10kV rated SiC IGBT can be reduced to below 2 MV.cm -1 , a prerequisite to achieve a high-degree of reliability in high-voltage power devices. We therefore propose that the retrograde p-well is highly promising for the development of>10kV SiC IGBTs

    The effect of interfacial charge on the development of wafer bonded silicon-on-silicon-carbide power devices

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    A new generation of power electronic semiconductor devices are being developed for the benefit of space and terrestrial harsh-environment applications. 200-600 V lateral transistors and diodes are being fabricated in a thin layer of silicon (Si) wafer bonded to semi-insulating 4H silicon carbide (SiC) leading to a Si/SiC substrate solution that promises to combine the benefits of silicon-on-insulator (SOI) technology with that of SiC. Here, details of a process are given to produce thin films of silicon 1 and 2 μm thick on the SiC. Simple metal-oxide-semiconductor capacitors (MOS-Cs) and Schottky diodes in these layers revealed that the Si device layer that had been expected to be n-type, was now behaving as a p-type semiconductor. Transmission electron microscopy (TEM) of the interface revealed that the high temperature process employed to transfer the Si device layer from the SOI to the SiC substrate caused lateral inhomogeneity and damage at the interface. This is expected to have increased the amount of trapped charge at the interface, leading to Fermi pinning at the interface, and band bending throughout the Si layer

    The optimization of 3.3 kV 4H-SiC JBS diodes

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    The article reports a comprehensive study optimizing the OFF- and ON-state characteristics of 3.3 kV junction barrier Schottky (JBS) diodes made using nickel, titanium, and molybdenum contact metals. In this design, the same implants used in the optimized termination region are used to form the P-regions in the JBS active area. The width and spacing of the P-regions are varied to optimize both the ON- and OFF-state of the device. All the diodes tested displayed high blocking voltages and ideal turn-on characteristics up to the rated current of 2 A. However, the leakage current and the Schottky barrier height (SBH) were found to scale with the ratio of Schottky to p + regions. Full Schottkys, without p + regions, and those with very wide Schottky regions had the lowest SBH (1.61 eV for Ni, 1.11 eV for Mo, and 0.87 eV for Ti) and the highest leakage. Those diodes with the lowest Schottky openings of 2 μm had the lowest OFF-state leakage, but they suffered severe pinching from the surrounding p + regions, increasing their SBH. The best performing JBS diodes were Ni and Mo devices with the narrowest pitch, with the p + implants/Schottky regions both 2 μm wide. These offered the best balanced device design, with excellent OFF-state performance, while the Schottky ratio guaranteed a relatively low forward voltage drop

    3.3 kV SiC JBS diodes employing a P2O5 surface passivation treatment to improve electrical characteristics

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    3.3 kV Schottky barrier diodes and Junction Barrier Schottky diodes have been fabricated, employing a phosphorous pentoxide (P2O5) surface treatment prior to metal deposition in an attempt to further condition the power device’s interface. For SBD structures, the treatment consistently reduces the leakage current in molybdenum, tungsten and niobium SBDs, for the tungsten treatment by more than four orders of magnitude. X-ray photoelectron spectroscopy (XPS) analysis on the treated SBD interface revealed formation of a metal phosphate between P2O5 and the metal. When compared to an untreated sample, the P2O5 treatment has increased the valence band to fermi level offset by 0.2 eV to 3.25 eV, indicating that the treatment results in a degenerately n-doped SiC surface. When applied to fully optimised 3.3 kV JBS power structures utilizing a hybrid JTE design, P2O5 treatments improved blocking capabilities across the entire dataset by as much as 1,000

    High-Voltage Integrated Circuits: History, State of the Art, and Future Prospects

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    Performance improvement of >10kV SiC IGBTs with retrograde p-well

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    A p-well consisting of a retrograde doping profile is investigated for performance improvement of >10kV SiC IGBTs. The retrograde p-well, which can be realized using low-energy shallow implants, effectively addresses the punch-through, a common issue in high-voltage vertical architectures consisting of a conventional p-well with typical doping density of 1e17cm-3 and depth 1μm. The innovative approach offers an extended control over the threshold voltage. Without any punch-through, a threshold voltage in the range 6V-7V is achieved with gate-oxide thickness of 100nm. Gate oxide thickness is typically restricted to 50nm if a conventional p-well with doping density of 1e17cm-3 is utilized. We therefore propose a highly promising solution, the retrograde p-well, for the development of >10kV SiC IGBTs

    Engineering the Schottky interface of 3.3 kV SiC JBS diodes using a P2O5 surface passivation treatment

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    A systematic study is presented into the impact of a P2O5 surface passivation treatment, carried out prior to the deposition of a high refactory metal contact to 3.3 kV JBS diodes. Electrical results from Mo, W and Nb diodes reveal that those diodes that undergo the treatment have a major leakage current reduction, most significantly by 3.5 orders of magnitude to 1.5×10-6 A.cm-2 for treated W diodes. When applied to fully optimized 3.3 kV Mo/SiC JBS diodes, the P2O5 surface passivation treatment reduces the apparent barrier height, as well as the leakage current. SIMS analysis reveals that during the treatment, phosphorous diffuses into the top 10 nm of the SiC, achieving a peak density of 1019 cm-3, while XPS results suggest some of this diffuses into the contact metal during the contact anneal, altering the SBH. TCAD simulations help give more insight into band diagram changes at the Schottky interface, where the partial activation of the phosphorous ions is shown to alter the Schottky barrier, promoting a thermionic field emission conduction, effectively lowering the barrier height at the interface in Mo/4H-SiC diodes
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