Dedicated front-end electronics for the next generation of linear collider electromagnetic calorimeter

This paper describes an R&D electronic program for the next generation of linear collider electromagnetic calorimeter. After a brief presentation of the requirements, a global scheme of the electronics is given. Then, we describe the three different building blocks developed in 0.35\mum CMOS technology: an amplifier, a comparator and finally the pipelined AD

PARISROC, a Photomultiplier Array Integrated Read Out Chip

PARISROC is a complete read out chip, in AMS SiGe 0.35 !m technology, for photomultipliers array. It allows triggerless acquisition for next generation neutrino experiments and it belongs to an R&D program funded by the French national agency for research (ANR) called PMm2: ?Innovative electronics for photodetectors array used in High Energy Physics and Astroparticles? (ref.ANR-06-BLAN-0186). The ASIC (Application Specific Integrated Circuit) integrates 16 independent and auto triggered channels with variable gain and provides charge and time measurement by a Wilkinson ADC (Analog to Digital Converter) and a 24-bit Counter. The charge measurement should be performed from 1 up to 300 photo- electrons (p.e.) with a good linearity. The time measurement allowed to a coarse time with a 24-bit counter at 10 MHz and a fine time on a 100ns ramp to achieve a resolution of 1 ns. The ASIC sends out only the relevant data through network cables to the central data storage. This paper describes the front-end electronics ASIC called PARISROC.Comment: IEEE Nuclear Science Symposium an Medical Imaging Conference (2009 NSS/MIC

Le Mécénat D'entreprise Face Aux Fusions-acquisitions: Nouveaux Ancrages, Nouvelles Perspectives

In 2001, l'Observatoire de la Générosité et du Mécénat conducted a survey on the impact of mergers and acquisitions on the sponsoring policies of 15 French and international companies. This report describes a second survey which was undertaken in 2003-2004 analysing 10 of the original companies to verify the accuracy of the conclusions from the initial survey

FLC−SIPM: Front-End Chip for SIPM Readout for ILC Analog HCAL

eConf: C050318 : LCWS-2005-0916An integrated front-end chip has been developed to readout the Silicon PM for the ILC analog hadronic calorimeter. It is built around a variable gain low-noise preamplifier followed by a variable peaking-time shaper (20-200 ns), track and hold and multiplexed output. This structure allows to produce single photo electron spectrum with well separated peaks for absolute calibration at fast shaping (40ns) as well as physics signals from the scintillating fibbers (up to 2000 photo-electrons) with a slower shaping (150ns) compatible with the W-Si Electromagnetic Calorimeter DAQ. Besides, an input DAC allows to tune the detector gain by varying the operating voltage by up to 5V. The chip accommodates 18 channels and 1000 circuits have been produced in 2004, the design and the measurement results of which will be presented

Front-end Electronic for the Calice ECAL Physics Prototype

eConf: C050318 : 0902A 18-channel low-noise front-end chip has been designed and produced to read out the 1cm² silicon PIN diodes of the CALICE WSi physics prototype calorimeter. Each channel includes a multi-gain low noise charge preamplifier followed by a bi-gain shaper and a track and hold device. A single output allows reading out every channel at 5 MHz through a multiplexer. Voltage swing is 2.5V with a 5‰ non-linearity. The measured dynamic range on a fixed gain is larger than 13 bits. The gain of the preamplifier can be tuned from 0.3V/pC to 5V/pC with 4 bits. The shaping is done by two fixed-gain shapers (gain 1 and gain 10). Output measured noise is 3000 e- with a detector capacitance of 100pF and a MIP around 42000 e-. Crosstalk is around 1‰. 1000 chips have been produced to equip the physics prototype. Several version of PCB have been designed, taking into account the thickness constraint. A first version with the front-end chip outside the detector has been produced and has been running since January 2005 at DESY, exhibiting an overall MIP/noise ratio of 9. A new thinner version embedding the chip inside the calorimeter has been prototyped and is ready to go in test beam

“ROC” Chips Readout

International audienceThe OMEGA group at LAL has designed 3 chips for ILC calorimeters: one analog (SPIROC) and one digital (HARDROC) for the hadronic one and also one for the electromagnetic one (SKIROC). The readout and the management of these different chips will be explained. To minimize the lines between the ASICs and the DAQ, the readout is made thanks to 2 lines which are common for all the chips: Data and TransmitOn. As the chips are daisy chained, each chip is talking to the DAQ one after the other. When one chip has finished its readout, it starts the readout of the chip just after. Moreover, during this readout, only the chip which is talking to the DAQ is powered: this is made thanks to the POD (Power On Digital) module in the ASIC. In the ILC mode, readout sequence is active during inter bunch crossing (like ADC conversion). Another chip designed for PMM2 R&D program (PARISROC) integrates a new selective readout: that's mean only hit channels are sent to the DAQ in a complete autonomous mode

EASIROC, an Easy & Versatile ReadOut Device for SiPM

AbstractEASIROC, standing for Extended Analogue Si-pm Integrated ReadOut Chip is a 32 channels fully analogue front end ASIC dedicated to readout SiPM detectors. This low power and highly versatile ASIC was developed from the chip SPIROC[1] which has been designed for the Analogue Hadronic Calorimeter foreseen at the International Linear Collider. EASIROC integrates a 4.5V range 8-bit DAC per channel for individual SIPM gain adjustment. A multiplexed charge measurement from 160 fC up to 320 pC is available thanks to 2 analogue outputs. These charge paths are made of 2 variable gain preamplifiers followed by 2 tuneable shapers and a track and hold. A trigger path integrates a fast shaper followed by a discriminator the threshold of which is set by an integrated 10-bit DAC. These 32 trigger outputs can be used for timing measurements. The power consumption is lower than 5 mW/channel and unused features can be powered OFF to decrease the power. The chip has been designed in AMS 0.35μm SiGe technology and 4000 dies have been produced in 2010. Its versatility allows its use in many photo detector experiments and is already used for PEBS, MuRAY, J-PARC and medical imaging