eConf: C050318 : LCWS-2005-0916An integrated front-end chip has been developed to readout the Silicon PM for the ILC analog hadronic calorimeter. It is built around a variable gain low-noise preamplifier followed by a variable peaking-time shaper (20-200 ns), track and hold and multiplexed output. This structure allows to produce single photo electron spectrum with well separated peaks for absolute calibration at fast shaping (40ns) as well as physics signals from the scintillating fibbers (up to 2000 photo-electrons) with a slower shaping (150ns) compatible with the W-Si Electromagnetic Calorimeter DAQ. Besides, an input DAC allows to tune the detector gain by varying the operating voltage by up to 5V. The chip accommodates 18 channels and 1000 circuits have been produced in 2004, the design and the measurement results of which will be presented

de La Taille, C.

Martin-Chassard, G.

Raux, L.

HAL-IN2P3

FLC–SIPM: Front-End Chip for SIPM Readout for ILCAnalog HCALG. Martin-Chassard, C. De La Taille, L. RauxTo cite this version:G. Martin-Chassard, C. De La Taille, L. Raux. FLC–SIPM: Front-End Chip for SIPM Readoutfor ILC Analog HCAL. Hewett J. 2005 International Linear Collider Worskhop (LCWS05), Mar2005, Stanford, United States. pp.684-691, 2005. <in2p3-00122909>HAL Id: in2p3-00122909http://hal.in2p3.fr/in2p3-00122909Submitted on 5 Jan 2007HAL is a multi-disciplinary open accessarchive for the deposit and dissemination of sci-entific research documents, whether they are pub-lished or not. The documents may come fromteaching and research institutions in France orabroad, or from public or private research centers.L’archive ouverte pluridisciplinaire HAL, estdestine´e au de´poˆt et a` la diffusion de documentsscientifiques de niveau recherche, publie´s ou non,e´manant des e´tablissements d’enseignement et derecherche franc¸ais ou e´trangers, des laboratoirespublics ou prive´s.2005 International Linear Collider Workshop - Stanford, U.S.A.FLC−SIPM: Front-End Chip for SIPM Readout for ILC Analog HCALC. de La Taille, G. Martin-Chassard, L. RauxIN2P3/ LAL, Orsay, 91898, FRANCEAn integrated front-end chip has been developed to readout the Silicon PM for the ILC analog hadronic calorimeter.It is built around a variable gain low-noise preamplifier followed by a variable peaking-time shaper (20-200 ns), trackand hold and multiplexed output. This structure allows to produce single photo electron spectrum with well separatedpeaks for absolute calibration at fast shaping (40ns) as well as physics signals from the scintillating fibbers (up to 2000photo-electrons) with a slower shaping (150ns) compatible with the W-Si Electromagnetic Calorimeter DAQ. Besides,an input DAC allows to tune the detector gain by varying the operating voltage by up to 5V. The chip accommodates18 channels and 1000 circuits have been produced in 2004, the design and the measurement results of which will bepresented.1. INTRODUCTIONA hadronic calorimeter prototype is now designing for ILC with scintillator tiles read by silicon photo-multipliers(fig. 1), developed by MEPhI and PULSAR[1]. Dimension of that prototype is around 1m3 with scintillator tiles from3 by 3 cm to 12 by 12 cm over 36 layers for high granularity. The silicon PM (SiPM) is a matrix of pixels directlycoupled to the tile (fig. 2) and the tiles are grouped to form a mini HCAL with around 10000 readout channels.Figure 1: Silicon photo-multiplier schematicFigure 2: tile with SiPMA front-end chip has been developed to read out 18 SiPM. This paper describe that chip (fig. 3) called “flc−sipm”.Its general architecture will be explained and measurements will be shown.1.1. SiPM electronic characterisationWhen the PM works with a gain of 106, the photo-electron is a signal of 160 fc and the MIP taken at 20 p.e. givesa signal of 3.3 pc. The maximum signal is around 120 MIPs so the input dynamic range of the circuit should be 400pc. The SiPM pulse shape is set by the wavelength shifter fibber : it is a very fast signal with a rise time of few0916Figure 3: “flc−sipm” chip layoutns. The noise rate is around 2MHz so a calibration is necessary on single photo-electron and must be done at fastshaping to avoid pile up.The SiPM gain varies a lot with high voltage value (It can go up to 7% for 100mV of high voltage variation). Tohave quite the same gain for each SiPM, we need to adjust the high voltage from 63 to 67 V, so a DAC (digital toanalog converter) is added on each channel of the chip to compensate for SiPM gain variation.2. PHYSICS CONTEXTIn the CALICE collaboration, the HCAL prototype[2] has to be added to the ECAL physics prototype for testbeam in DESY mid 2005 and going on in higher energy beam in 2006. The chip has been designed in a very tightschedule in order to be ready in time with the HCAL prototype.2.1. SiPM electronic characterisationWhen the PM works with a gain of 106, the photo-electron is a signal of 160 fc and the MIP taken at 20 p.e. givesa signal of 3.3 pc. The maximum signal is around 120 MIPs so the input dynamic range of the circuit should be 400pc.The SiPM pulse shape is set by the wavelength shifter fibber : it is a very fast signal with a rise time of few ns.The noise rate is around 2MHz so a calibration[3] is necessary on single photo-electron and must be done at fastshaping to avoid pile up.The SiPM gain varies a lot with high voltage value (It can go up to 7% for 100mV of high voltage variation). Tohave quite the same gain for each SiPM, we need to adjust the high voltage from 63 to 67 V, so a DAC (digital toanalog converter) is added on each channel of the chip to compensate for SiPM gain variation.2.2. SiPM connection to the chipThe SiPM is directly connected to the chip as shown in fig. 4. The high voltage is provided by the cable shielding.There is no external circuitry except high voltage decoupling and cable matching components. The DAC comesdirectly at the chip input and it is necessary to filter its noise.0916Figure 4: SiPM connection to the readout3. CHIP DESCRIPTION3.1. General descriptionThe flc−sipm is an 18 channel charge input front-end circuit. It provides a shaped signal proportional to the inputcharge. The chip houses 18 channels made of a low noise variable-gain charge preamplifier followed by a CRRC2shaper with a variable shaping time. Each of the shaper output comes into a track and hold system giving a singlemultiplexed output. The bias of each stage is common for 18 channels. An 8-bit DAC is in parallel to the preamplifierinput.The total power consumption of the chip is around 200mW with 5V supply voltage. The chip is designed in a0.8?m CMOS technology of AMS[4] and has an area of 10 mm2 (fig. 3). Around 1000 circuits have been producedat the end of 2004 and are packaged in a QFP100 case.3.2. One channel descriptionThe channel architecture is shown in fig. 5At the input of each channel, there is an 8-bit DAC to provide 5V of DC voltage change, it is coupling with acapacitor at the input of the preamplifier. This capacitance is also used for high voltage decoupling and it is followedby a resistor in order to make a first derivative constant time. For speed and noise reasons, this resistor could beshorted.A low noise charge preamplifier follows : it gives 1300 electrons of noise at fast shaping compared to the 106electrons given by a single photo-electron. The gain of this preamplifier (feedback capacitance) can be externallychosen on 4 bits : it varies from 0.7 to 10 V/pc.The filtering is done by a CRRC2 shaper with variable time constant which can be externally chosen on 4 bitsfrom 12 to 180 ns. The fast shaping (called calibration mode) is used for SiPM calibration on single photo-electronand the long shaping (called physics mode) is necessary to be compatible with the ECAL readout.3.3. DAC descriptionThe DAC used is an 18 channel 8-bit DAC, its structure is based on scaled current mirrors. It provide 5V ofexcursion in order to adjust the high voltage value and then the SiPM gain. Its output comes at the preamplifier0916Figure 5: Channel architectureinput so we had a 5K series resistor (fig. 4) in order to filter the DAC noise : with the DAC on the RMS noise go upfrom 1.2mV to 1.25mV at fast shaping (12ns).4. MEASURED PERFORMANCES4.1. Preamplifier noiseThe fig. 6 shows the preamplifier noise measurement in electron versus shaping time constant. In calibration mode,the RMS noise is around 1.25 mV with the input resistor shorted. In physics mode, this input resistor is used toobtain a long shaping time but the RMS noise remains less than 1 mV.4.2. DAC linearityThe linearity of the 18 channels of the DAC is shown in fig.7: the non-linearity, around 2%, is essentially due tomismatch in current mirrors and is enough to adjust correctly the high voltage for SiPM gain.4.3. Calibration modeThe figure 8 shows the response of the circuit for a single photo-electron at the input (0.6mV injected thru 270pF)with various fast shaping time. The gain of the preamplifier is taken at 5V/pc (the feedback capacitance is 0.2pF)and the input resistor is shorted. At 12ns of shaping, a single photo-electron gives a signal of 11mV with a peak at35ns.0916Figure 6: preamp noiseFigure 7: 18 channel DAC linearity and residuals4.4. Physics modeIn physics mode, we take a long time constant (180 ns), a gain preamplifier of 2.5 V/pc (the feedback capacitanceis 0.4pF) and the input resistor is used. In these conditions, a MIP electronically injected (without detector and with9.5mV in 270pF) gives at the output a signal of 23mV with a peak at 160ns as shown in fig. 9.4.5. Cross-talk considerationsThe cross-talk between channels was measured and it is negligible (less than 0.2%). Fig. 11 shows output ofone channel with signal at input compared to neighbour and non-neighbour outputs without signal at input andmultiplied by 100.The neighbour channel shows the capacitive coupling contribution and the non- neighbour channel shows the longdistance cross-talk due to common reference voltage on chip.0916Figure 8: SPE response at various shaping time4.6. Spectrum measurementsConnecting the SiPM to our chip we can clearly observe peaks for 1 photo-electron, 2 p.e., 3 p.e. and so on asshown in fig. 12.5. SCHEDULE AND COSTThe development of this chip was very short. The first prototype was submitted in June 2004. After test andvalidation of this prototype, a production of 1000 chips stated in November 2004. The production was delivered inJanuary 2005, all chip are now under tested and will be available for the CALICE collaboration in April 2005.The overall cost of this production is around 25 K (or 20 K$), the biggest part is for silicon dies and 4 K forpackages.6. CONCLUSIONA series of 1000 chips with 18 channels each has been produced in less than one year. It is a very versatile chipwith variable gain preamplifier (from 0.7 to 10 V/pc) and with variable shaping time shaper (from 12 to 180 ns).In calibration mode, the fast shaping clearly separates single photo-electron peaks. In physics mode, the dynamicrange of 11bits (1mV to 2V) fulfils the SiPM requirements and remains compatible with the ECAL readout.An 8-bit DAC provides 5V excursion of change in high voltage value and allows to adjust the SiPM gain.References[1] M. Danilov, these proceedings.[2] F. Sefkow, these proceedings.[3] E. Garutti, these proceedings.[4] www.austriamicrosystems.com0916Figure 9: MIP response in physics mode conditionsFigure 10: linearity versus MIP injection for various preamplifier gains and residuals for gain 0.4pF0916Figure 11: Cross-talk measurement in physics mode conditionsFigure 12: SPE spectrum measurement in physics mode conditions0916

FLC−SIPM: Front-End Chip for SIPM Readout for ILC Analog HCAL

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