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OVERVIEW OF ATLAS LAr RADIATION TOLERANCEC. de La Taille, LAL, Orsay, France (email: taille@lal.in2p3.fr)AbstractThis document reviews the various developmentspursued by the liquid argon (LAr) community in order toensure the radiation tolerance of its front-end electronics.1. INTRODUCTIONThe LAr front-end electronics is located right on thecryostat in dedicated front-end crates [1]. These housefour different species of boards :• Front-end boards (FEB) which bear preamplifiers,shapers, analog memories, ADCs and optical outputs.• Calibration boards to generate 0.2% accuracycalibration pulses• Tower builder boards (TBB) which perform analogsummation and re-shaping for LVL1 trigger• Controller boards which handle TTC and serial link(SPAC) control signalsAll these boards have been produced in severalexemplars in order to equip module 0 calorimeter andextensively used in the testbeam for the last two years.Their performance has met the requirements in terms ofsignal, noise, density at the system level on severalthousands of channels [2]. However, they make use ofmany COTS, in particular FPGAs that are not radiationtolerant.Since then, several developments have been realised inorder to design the “final” ATLAS boards, based on thesame architecture but completely radiation tolerant. Amilestone has been set to get the first boards by mid-2001and a full crate by the end of 2001. The full productionshould be launched in 2002 (at least for the FEBs) and theinstallation would take place in 2004.The radiation levels anticipated at the Lar crate locationis 50 Gy in 10 years and 1.6 1013 N/cm2 [3]. Taking intoaccount the safety factors required by the rad-tol policy[4] , they must be qualified up to 0.2-3 kGy (20-300 krad)and 1-5 1013 N/cm2, depending on the process as explainedin [5] of these proceedings.These developments will now be exposed, board byboard, with a particular attention to the single eventeffects (SEE), their impact at system level and theirmitigation.2. FRONT-END BOARDS  [6]The various components used on the module front-endboards (FEB0) are shown in Figure 1.2.1  Preamplifiers and shapersThe preamplifiers (0T) are hybrids built around discretehigh FT bipolar transistors. They have been irradiatedseveral times (alone or with the shaper below) and havenot shown any change of performance after 2 kGy and5.1013 N/cm2 [7]. For the hadronic end-cap, GaAsmonolithic preamps are used inside the LAr and havewithstood  1014N [8].The shapers are monolithic 1.2 m BiCMOS circuitsfor which the radiation tolerance has been attempted at thedesign phase by using mostly the fast NPN transistors.The MOS are used mainly as overdriven static switches[9]. Notwithstanding, they have passed numerousirradiation tests without experiencing changes in gain orpeaking time, as can be seen in Figure 2. The shaper alsoincorporates a simple logic to deactivate noisy channels inthe trigger sums, for which SEU is not critical.Furthermore, a possible sensitivity to latch-up was feared,although never observed in 10 MeV neutrons tests atCERI. For safety, an anti-latchup resistor has been addedin the logic power supply line.Figure 1  : Synoptic diagram of the Front-end board used in module 0 test beamFigure 2 :  Shaper amplitude and peaking time undergamma and neutron irradiation.2.2 Switched Capacitor Arrays (SCA)The analog pipelines (SCA) which follow theshapers have been designed from the start in DMILLradiation hard technology. They make use only of theCMOS components and of full custom logic running at40 MHz. Several prototypes have been realized inDMILL in the last 3 years, as well as in radiation softtechnologies (AMS 0.8 m, HP 0.6 m) with similarelectrical performance. These results and the irradiationresults can be found in these proceedings [10]. Thelatest batch has suffered from a very low yield (10%)due to a few randomly distributed leaky switches. Thisprocess defect has subsequently been understood andfixed in a later batch. The chip will undergopreproduction run by the end of 2000.2.3 SCA controllerThe read and write addresses necessary to operatethe SCA with no dead time are generated by a SCAcontroller. In module 0 FEB, these functions wereimplemented in a  XC4036 Xilinx, based on 0.35 mtechnology [11]. This component has been tested forradiation tolerance and has shown a significant supplycurrent increase after 400 Gy, as shown in Figure 3.It has then been decided to migrate this element intoDMILL. However, the chip complexity and criticaltimings have turned out to be marginally achieved andresulted in a very large chip area (100mm2) for whichthe yield is likely to be rather small (20%).  Besides,due to the large area, it has not been possible to includeany error correction mechanism, leaving the SEUproblem open.  For such chip, the SEU effects arerather serious as read or write pointers could getsystematically wrong. A possible fallback in 0.25 mtechnology is now being designed, including SEU errorcorrection logic.2.4 ADC and gain selectorThe SCA is followed by a 12 bit 5 MHz ADC. ForFEB0, AD9220 was used but has also failed total dosetests. We therefore plan to use the AD9042, which hasbeen qualified by CMS [12].Two ADCs feed a gain selector chip that chooses thecorrect gain and formats the data for the subsequentRODs. As the chip stores two thresholds per channelfor the gain selection, SEU have been mitigated with aHamming correction code. It results in a  20 mm2ASIC, to be submitted to DMILL in september 2000.Date Dose Duration # channelsMay 97 2 1013 N 2 days 2 chOct 97 2 kGy 4 days 2 chJul 98 1014 N 1 day 8*3Sept 98 2 kGy 4 days 16*3Jul 99 2 kGy 2 months 32*3Oct 99 2 1013 N 2 days 32*3Figure 3:  Supply current after gamma irradiation forthe Xilinx XC40362.5 Optical outputThe formatted digital data are sent out after LVL1trigger through an optical fiber. Five samples of each128 channels are multiplexed at 40 MHz, resulting in2.6 Gbit/s output rate. The baseline option was usingHP Glink, but extensive irradiation studies [13] haveshown that although the link exhibited very good totaldose tolerance up to 43 kGy and 1013 N, it was sensitiveto SEU, 0.05 error/link/hour with ATLAS spectrum. Inparticular, energetic neutrons could inducesynchronization errors, bringing the link down up to 10ms.Several options have been studied in order tocircumvent this problem and can be found in theseproceedings [14]. One consists in using two Glinks anda “smart switch” at the receiving end, whereas anotheris based on GaAs link and sending twice the data.Slightly after the conference, the choice has been madeto stay with the single Glink for cost reasons.Another digital chip (MUX) is then necessary to turnthe 32bit 40 MHz data into 16bit 80 MHz Glink inputformat. This chip has been submitted in DMILL in may2000.3. CALIBRATION BOARD  [15]3.1  Low offset opamps and 16bit DACAs shown in Figure 4, the precision current source isbuilt around a low offset opamp and a 0.1% precision 5Ohm resistor. The opamp offset should not be largerthan the DAC LSB=16 V. In previous prototypes,OP07 were used and several similar opamps have beentested [16] to 2 kGy and 2.1013 N/cm2, as shown in thetable below. None has been good enough to bequalified for ATLAS.It has therefore been decided to develop a fullcustom rad-hard circuit to perform this function. Twoapproaches have been pursued :• A static low offset opamp based on centroidbipolar transistors and fuse trimming• An auto-zero opamp [17] in which the offset isstored in a 10 nF capacitor.Prototypes of each version have been realized inAMS 0.8 m BiCMOS, before being translated intoDMILL. The static opamp has been submitted in may2000, whereas the autozero could be submitted early2001. The retained architecture will be chosen uponirradiation test results.A 16bit DAC with 10-bit accuracy is necessary tocover the full dynamic range of ATLAS, but two COTStested have seen the offset rise to 5 mV after only 20Gy. Therefore, a 16 bit R/2R ladder DAC has beenmade with 16 switched identical current mirrors andexternal precision resistors (0.1%). To reduce thesensitivity to Vbe mismatch and variations withtemperature the emitters of the current sources arestrongly degenerated. This ladder DAC has beendeveloped and tested successfully in AMS 0.8BiCMOS and submitted to DMILL in may 2000, withimproved temperature stability (1 V/K).Type Voff before Voff after Ibias before  Ibias afterOP 113 7-60 V 4-160 V 0.35 A 2 AOP 177 30 V 4-160 V 0.7 nA 70-90 nAAD 829 60-200 V 130 V 3.5 nA 4.5 ALT1097 1-12 V 1200 V 0.1 nA 100 nAOP 77 10-20 V 70-190 V 1 nA 100 nALT 1028 5-10 V 70-360 V 10-25 nA 5-80 nAOP 27 1-10 V 40-100 V 1-50 nA 0.7-0.9 AOP 07 5-15 V 0.1-0.5mV 0.1-0.4 nA 0.2-0.3 AFigure 4 :  Synoptic diagram of the calibration board used on Module 0 tests.3.2  Control logicThe calibration boards used on module 0 werecontrolled by an elaborate digital circuitry whichallowed to load on board a full calibration sequence(ramping the DAC, changing patterns…). Althoughpractical and very time efficient this circuitry wasbased on memories and numerous FPGAs which wouldnot operate reliably in the high radiation environment.It has thus been decided to simplify the control logicand load through the SPAC serial bus the runparameters (DAC value, delays, and pulsing patterns).These parameters are decoded from I2C local bus andstored in  registers, which have again been designed inDMILL. No particular SEU mitigation has beenincluded, as the calibration board is idle 99% of thetime and SEU results only in a wrong calibration pulse,which can be discarded in the RODS.4.  TOWER BUILDER BOARDThe tower builder board is used to perform theanalog sum of the different sampling depths of thecalorimeter in order to get the total energy in a 0.1x0.1tower. This signal is then sent through shielded twistedpairs to the LVL1 trigger processor. As the signalsfrom the calorimeter exhibit different shapes across thecalorimeter (due to different detector capacitance), apole-zero unit is used to compensate for it and touniformize the waveforms so that they can be summed.Furthermore, an anlog delay line is used to align thewaveforms in time and compensate for different cablelengths or particle time of flight.An analog multiplexer is used in order to select thecorrect tap on the delay line. Following negative testson previous commercial multiplexers (DG358) whichfailed at 170 Gy, a DMILL chip has been developed in1998. This chip called BiMUX includes 8 large CMOSswitches (200/0.8 m) and a simple address decoder toactivate them. It has been fabricated in 1999 with ayield of 85% and tested successfully, including toradiation doses up to 2 kGy and 3 1013 N/cm2.Finally, the board makes use of commercial fastopamps (HFA1135, AD8011) which have also beentested successfully up to 2 kGy and 3 1013 N/cm2, butadditional tests against SEE are foreseen.5.  CONTROLLER BOARDEvery half crate is controlled by a controller boardwhich receives optically the TTC signals (clock, LVL1,BCR…) and the serial link (SPAC) to write and readparameters on the various boards. These signals aretranslated to electrical signals and distributed to all theother boards, point to point for TTC and on a G10 busfor the SPAC. For reliability all the SPAC lines aredoubled (including the incoming optical fibers) and theselection of the active line is performed in the controlroom.On each board (including the controller) the SPACsignals are decoded by a SPAC slave chip which hasalso been realized in DMILL in may 2000. This chip isdescribed in these proceedings [18].Figure 5: Synoptic diagram of the tower builder board.6. CONCLUSIONThe liquid argon calorimeter front-end electronicshas been finalized and tested successfully in test beam.The analog front-end elements (preamp, shapers,analog pipelines) have shown radiation tolerance inexcess of the ATLAS requirements, including thesafety factors. The digital circuits (FPGAs) have failedsuch tests and have now been migrated into DMILLASICs. The use of this radiation hard technology willlargely alleviate the burden of the radiation tests. Intotal, almost 10 new DMILL chips will be necessary, assummarized in the table below :Chip Area(mm2)NumberneededNumberproducedSubm.protoSCA 30 54,400 80,000 98,99,00SCA contr. 100? 3,400 20,000 Nov 00?Gain select 21 13,800 20,000  Sept 00Config contr 20 3,400 5,000 Sept 00MUX 18 1,700 2,500 Sept 00SPAC slave 27 2,200 3,300 May 00Opamp 1.8 16,900 30,000 May 00DAC 6.3 130 200 May 00Delay 6.5 260 350 99Calib logic 16 910 1500 May 00BiMUX 4.6 8,320 11,000 99Among these chips, the SCA controller is now themost critical and problematic in DMILL, a backupsolution in 0.25 um is being considered.Although avoided as much as possible, some COTSremain necessary (fast opamps, ADCs) for which theprocurement plan and radiation qualification need to befinalized to minimize the associated risks.The goal is now to produce the first final (radiationtolerant) ATLAS front-end board by mid 2001 andhave a full crate (all board types) by spring 2002.7. REFERENCESThe transparencies can be found on  :http://atlasinfo.cern.ch/Atlas/GROUPS/LIQARGON/CONFERENCE/electalk.html[1]  LAr technical design report. CERN/LHCC/98-016[2]  J. Colas  : overview of the ATLAS LArGelectronics. CERN/LHCC/99-33 (LEB5Snowmass)  p 217-221[3]  M. Schupe : july 2000 radiation maps in [4][4]  ATLAS policy for radiation hardness.http://atlas.web.cern.ch/Atlas/GROUPS/FRONTEND/radhard.html[5]  M. Dentan : overview of ATLAS radiation policy.On radiation tolerant electroncis. LEB6 (Krakow)[6]  D. Breton et al. : the front-end board for theATLAS liquid Argon calorimeter.CERN/LHCC/98-36 (LEB4  Rome)  p 207-212[7]  M. Citterio et al. : the ATLAS calorimeterpreamplifier… LEB5 (Snowmasss) p 237-241[8]  H. Brettel et al. : cold electronics for the liquidargon hadronic end-cap calorimeter of ATLAS.LEB5 (Snowmass) p 227-231[9]  J.Collot et al. : The Lar tri-gain shaper. ATLASinternal note : LArG 98-092[10]  D. Breton et al. :  HAMAC a rad-hard highdynamic range analog memory for Atlascalorimetry  LEB6 (Krakow)[11]  D. Gingrich et al. : total ionizing dose effects in aXilinx FPGA. ATLAS internal note : LArG 99-003[12]  P. Denes : digitization and data transmission forthe CMS electromagnetic calorimeter. LEB4(Roma) p 223-228[13]  M.L. Andrieux et al.. ATLAS internal note :LArG 00-006[14]  B. Dinkespieler : Redundancy or GaAs ? twodifferent approaches to solve teh problem of SEUin digital optical links.  LEB6 (Krakow)[15]  G. Perrot et al. : .the ATLAS calorimetercalibration board. LEB5 (Snowmass) p 265-269[16]  J. Colas et al.. : The LarG calibration boardATLAS internal note : LarG-99-026[17]  E. Marshalkowsi et al. : an integrated system forthe liquid argon calorimtery. ATLAS internalnote : LArG-99-013[18] B. Laforge : implementation of a Serial Protocolfor the liquid argon Atlas calorimeter (SPAC).LEB6 (Krakow)

Overview of ATLAS LAr radiation tolerance

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