CONTREX: Design of embedded mixed-criticality CONTRol systems under consideration of EXtra-functional properties

The increasing processing power of today’s HW/SW platforms leads to the integration of more and more functions in a single device. Additional design challenges arise when these functions share computing resources and belong to different criticality levels. CONTREX complements current activities in the area of predictable computing platforms and segregation mechanisms with techniques to consider the extra-functional properties, i.e., timing constraints, power, and temperature. CONTREX enables energy efficient and cost aware design through analysis and optimization of these properties with regard to application demands at different criticality levels. This article presents an overview of the CONTREX European project, its main innovative technology (extension of a model based design approach, functional and extra-functional analysis with executable models and run-time management) and the final results of three industrial use-cases from different domain (avionics, automotive and telecommunication).The work leading to these results has received funding from the European Community’s Seventh Framework Programme FP7/2007-2011 under grant agreement no. 611146

Sizing the role of London dispersion in the dissociation of all-meta tert-butyl hexaphenylethane

The chapel, showing frescos in the vault; The original basilica of Ss. Quattro Coronati (four crowned martyrs) was founded towards the end of the sixth century. It stands on the north side of the Coelian hill (Celio) in Rome, and is made up of several buildings grouped around the basilica. Traces of frescoes, mainly from the 13th and 14th centuries, and some columns from the nave of the early church were brought to light during restoration work in 1913-1914. When the chapel of St. Sylvester (1247) was acquired in 1570 by the Confraternity of the Marmorari (marble workers), whose patrons were the four saints, the presbytery was restructured in its present form with frescoes probably carried out by Raffaellino da Reggio. The members of the confraternity also commissioned the frescoes adjacent to the side entrance of the chapel, beneath the west portico of the first courtyard, showing the Visitation of Mary and the Nativity, dated 1588. Source: Santi Quatto Coronati Monastery [website]; http://www.santiquattrocoronati.org/ (accessed 1/20/2008

Experimental Evaluation of SAFEPOWER Architecture for Safe and Power-Efficient Mixed-Criticality Systems

With the ever-increasing industrial demand for bigger, faster and more efficient systems, a growing number of cores is integrated on a single chip. Additionally, their performance is further maximized by simultaneously executing as many processes as possible. Even in safety-critical domains like railway and avionics, multicore processors are introduced, but under strict certification regulations. As the number of cores is continuously expanding, the importance of cost-effectiveness grows. One way to increase the cost-efficiency of such a System on Chip (SoC) is to enhance the way the SoC handles its power consumption. By increasing the power efficiency, the reliability of the SoC is raised because the lifetime of the battery lengthens. Secondly, by having less energy consumed, the emitted heat is reduced in the SoC, which translates into fewer cooling devices. Though energy efficiency has been thoroughly researched, there is no application of those power-saving methods in safety-critical domains yet. The EU project SAFEPOWER (Safe and secure mixed-criticality systems with low power requirements) targets this research gap and aims to introduce certifiable methods to improve the power efficiency of mixed-criticality systems. This article provides an overview of the SAFEPOWER reference architecture for low-power mixed-criticality systems, which is the most important outcome of the project. Furthermore, the application of this reference architecture in novel railway interlocking and flight controller avionic systems was demonstrated, showing the capability to achieve power savings up to 37%, while still guaranteeing time-triggered task execution and time-triggered NoC-based communication