1,253 research outputs found
Mandibular rehabilitation: study of alternative concepts for implant-supported mandibular prosthesis
Inference in credal networks: branch-and-bound methods and the A/R+ algorithm
AbstractA credal network is a graphical representation for a set of joint probability distributions. In this paper we discuss algorithms for exact and approximate inferences in credal networks. We propose a branch-and-bound framework for inference, and focus on inferences for polytree-shaped networks. We also propose a new algorithm, A/R+, for outer approximations in polytree-shaped credal networks
Competitividade e défice externo da economia portuguesa
Mestrado em EconomiaA actual crise económica que Portugal enfrenta é o resultado do acumular de
excessos públicos e privados financiados até então com dÃvida,
essencialmente, externa. Este nÃvel de endividamento assume maior
representatividade pelo facto de não ter sido compensado por um crescimento
económico igualmente proporcional. Portanto, é vital fomentar o crescimento
económico futuro, não só para reduzir o peso da dÃvida, mas também para
uma maior sustentabilidade financeira. Assim, a primeira questão que se
coloca é: como que se potencia o crescimento económico? Uma das formas
de o conseguir é seguramente através do aumento da competitividade.
A competitividade, num âmbito geral, é essencial não só para o aumento das
exportações e crescimento das empresas, mas também para a atractividade
de investimento, para a criação de emprego, e para um maior bem-estar social
de um paÃs. Desta forma, a principal motivação desta dissertação foi analisar e
identificar que factores contribuÃram para a deterioração da competitividade e
condicionaram o progresso da economia portuguesa nos últimos 15 anos. Para
tal, efectuou-se uma análise evolutiva de variáveis sustentadas pela literatura
como determinantes da competitividade externa. Posteriormente, procedeu-se
a estimações pelo método dos MÃnimos Quadrados Ordinários para analisar
que variáveis influenciaram a deterioração do défice externo e da
competitividade externa portuguesa nos perÃodos considerados, pois a
persistência de elevados défices externos é suportada pela literatura como o
indicador mais evidente de perda de competitividade externa e de
desequilÃbrios macroeconómicos a longo-prazo. Os resultados obtidos nas
estimações permitem concluir que, nos perÃodos analisados, o preço do
petróleo, o efeito Balassa-Samuelson e a taxa de câmbio real deflacionada
pelos custos unitários do trabalho possuem uma relação negativa com o saldo
da balança de conta corrente, ou seja, um aumento destas variáveis contribuiu
para um agravamento do défice externo, e, assim, para a deterioração da
competitividade externa. Inversamente, as variáveis crédito ao sector privado
não-financeiro e flexibilidade salarial possuem uma relação positiva com o
saldo da balança de conta corrente, ou seja, uma deterioração destas variáveis
contribuiu para o agravamento do défice externo e da competitividade externa.The current economic crisis that Portugal is facing is the result of the
accumulation of public and private imbalances that were mainly supported by
external debt. This level of indebtedness becomes even more alarming and
unsustainable because it has not been offset by an equally proportional
economic growth. It is therefore essential to promote future economic growth,
not only to reduce the debt burden, but also to ensure financial sustainability.
Therefore, the first question that arises is how to enhance economic growth?
One way to achieve this is certainly through improving external
competitiveness. Competitiveness, in a general context, is essential not only to
increase exports and enterprise’s growth, but also to enhance the
attractiveness of investment, job creation, and thus to a more sustainable
economic welfare of a country . Thus, the main motivation of this dissertation is
to analyze and identify factors that contributed to the deterioration of
competitiveness and conditioned the progress of the Portuguese economy in
the last 15 years.
With this purpose was made an evolutive analysis in order to verify a series of
variables supported by the literature as determinants of external
competitiveness. Afterwards, we proceeded to estimates through the method of
Ordinary Least Squares in order to analyze variables that influenced the
deterioration of Portugal’s external deficit and external competitiveness. Once
the persistence of high levels of external deficits is supported by the literature
as the most obvious indicator of loss of external competitiveness and
macroeconomic imbalances unsustainable in the long term. From the results
obtained in the estimations we conclude that in the periods analyzed oil prices,
Balassa-Samuelson effect and the real effective exchange rate deflated by unit
labor costs have a negative relationship with the current account balance, i.e.,
an increase in these variables contributed to a higher external deficit, and thus
to the deterioration of external competitiveness. On the other hand, the
variables credit to the private sector and wage flexibility have a positive
relationship with the current account balance, i.e., a deterioration of these
variables contributed to higher external deficits and external competitiveness
deterioration
Prefilter Bandwidth Effects in Asynchronous Sequential Symbol Synchronizers based on Pulse Comparison by Hybrid Transitions at Quarter Bit Rate
This work studies the prefilter bandwidth effects in four asynchronous sequential symbol synchronizers. We consider three prefilter bandwidths namely B1=Â¥, B2=2.tx and B3=1.tx, where tx is the bit rate. The synchronizer has two variants one asynchronous by both transitions at bit rate and other asynchronous by hybrid (both and positive) transitions at quarter bit rate. Each variant has two versions namely the manual and the automatic. The objective is to study the prefilter with the four synchronizers and to evaluate their output jitter UIRMS (Unit Interval Root Mean Square) versus input SNR (Signal Noise Ratio).University of Beira Interiorinfo:eu-repo/semantics/publishedVersio
Phase Synchronism Loops of Carrier and Data
This work presents a Phase Lock Loop for Carrier Wave (CPLL) and a Phase Lock Loop for Data Bits (DPLL). Each one of these devices is constituted by a phase comparator, a loop gain, a low pass filter and a voltage controlled oscillator. The objective is to study these synchronizers and evaluate their performance in presence of noise. We measure the output jitter UIRMS (Unit Intervals Root Mean Square) versus input SNR (Signal Noise Ratio).University of Beira Interiorinfo:eu-repo/semantics/publishedVersio
Prefilter bandwidth effects in carrier phase synchronizers
This work studies the effects of the prefilter bandwidth on the carrier phase synchronizers.
We apply three different prefilter bandwidth namely B1=Â¥ (infinite), B2=2.tx and B3=1.tx, where tx is the transmissionrate.
We consider also four carrier wave phase synchronizers namely the analog (ana), the hybrid (hib), the combinational (cmb) and the sequential (seq).
The objective is to study the prefilter bandwidth with the four carrier synchronizers and to evaluate their output jitter UIRMS (Unit Interval Root Mean Square) versus input SNR (Signal to Noise Ratio).University of Beira Interiorinfo:eu-repo/semantics/publishedVersio
Data phase synchronizers of closed loop
This work studies the data phase synchronizers of closed loop or data phase lock loop (DPLL). This synchronizer have all its blocks inside of the loop, for this reason it is called closed loop. The synchronizer is a loop with a phase comparator and VCO (Voltage Controlled Oscillator), that synchronizes the output feedback with the main input data. We consider four data synchronizers namely the analog, the hybrid, the combinational and the sequential. The objective is to study the four synchronizers and to evaluate their output jitter UIRMS (Unit Interval Root MeanSquare) versus input SNR (Signal to Noise Ratio).University of Beira Interiorinfo:eu-repo/semantics/publishedVersio
Carrier phase synchronizers
This work studies four carrier phase synchronizers (CPS) or carrier Phase Lock Loop (CPLL). The
synchronizers are based in a loop with VCO (Voltage Controlled Oscillator) that synchronizes the output feedback with the input. We consider four carrier synchronizers namely
the analog, hybrid, combinational and sequential. The difference between them is in the phase comparator. The main objective is to study the synchronizers output jitter UIRMS (Unit Interval Root Mean Square) versus input SNR (Signal to Noise Ratio).University of Beira Interiorinfo:eu-repo/semantics/publishedVersio
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