This work studies the data phase synchronizers of closed loop or data phase lock loop (DPLL). This synchronizer have all its blocks inside of the loop, for this reason it is called closed loop. The synchronizer is a loop with a phase comparator and VCO (Voltage Controlled Oscillator), that synchronizes the output feedback with the main input data. We consider four data synchronizers namely the analog, the hybrid, the combinational and the sequential. The objective is to study the four synchronizers and to evaluate their output jitter UIRMS (Unit Interval Root MeanSquare) versus input SNR (Signal to Noise Ratio).University of Beira Interiorinfo:eu-repo/semantics/publishedVersio

Carvalho, José Pacheco de

Gameiro, Atilio

Reis, António

Rocha, José Ferreira da

English

UBibliorum repositorio digital da ubi

   Abstract— This work studies the data phase synchronizers of closed loop or data phase lock loop (DPLL). This synchronizer have all its blocks inside of the loop, for this reason it is called closed loop. The synchronizer is a loop with a phase comparator and VCO (Voltage Controlled Oscillator), that synchronizes the output feedback with the main input data. We consider four data synchronizers namely the analog, the hybrid, the combinational and the sequential. The objective is to study the four synchronizers and to  evaluate their output jitter UIRMS (Unit Interval Root Mean Square) versus input SNR (Signal to Noise Ratio). Index Terms—Synchronism, Digital Communications  I. INTRODUCTION This work studies the data phase synchronizers of closed loop. It is designed closed loop since all its components are inside the loop [1, 2, 3, 4, 5, 6, 7]. This synchronizer is a data Phase Lock Loop (DPLL) based in a phase comparator and VCO (Voltage Controlled Oscillator) that synchronizes the VCO output clock feedback with the main input data transitions [8, 9, 10, 11, 12]. We consider four synchronizers which are the analog (DPLL_ana), hybrid (DPLL_hib), combinational     (DPLL_cmb) and sequential (DPLL_seq) [13, 14, 15]. The data phase synchronizers of closed loop have three blocks which are the input adapter circuit, the clock recovery and the output decision circuit. The synchronizers DPLL_ana, DPLL_hib, DPLL_cmb need the adapter circuit, but the DPLL_seq synchronizes its VCO output clock directly by the input data transitions.  The adapter, in data transitions, generates a previous pulse of half period T/2, for posterior synchronism The clock recovery recoveries the clock. The decision samples and retimes the data (Fig.1).   Fig.1 Blocks of the closed loop data phase synchronizer  The DPLL has the phase comparator gain Kf, the loop filter F(s), the VCO gain Ko and Ka is the loop gain factor that controls the root locus and then the loop characteristics. In the prior and actual art - state, was developed various synchronizers, now it is need to know their performance.  The motivation is to study new synchronizers. This contribution increases the knowledge about synchronizers.   Manuscript received March 20, 2018; Supports from UBI and FCT. A. D. Reis is with the University of Beira Interior Covilha and Group of A. P. and Telecommunications, Portugal (e-mail: adreis@ ubi.pt). J. F. Rocha is with the University of Aveiro and Institute of Telecommunications, Portugal (e-mail: frocha@ ua.pt). A. S. Gameiro is with the University of Aveiro and Institute of Telecommunications, Portugal (e-mail: amg@ ua.pt). J. P. Carvalho is with the University of Beira Interior Covilha and Group of A. P. and Telecom., Portugal (e-mail: pacheco@ ubi.pt).  Following, we present the four closed loop data phase synchronizers: analog, hybrid, combinational and sequential. After, we present the project and tests. Then, we present the results. Finally, we present the conclusions.  II. FOUR SYNCHRONIZERS OF CLOSED LOOP This synchronizer has all its components inside of the loop. We consider four types namely the analog, the hybrid, the combinational and the sequential [1, 2]. The difference between them is in the phase comparator since the others blocks are equal.  A. Analog closed loop data synchronizer  The analog closed loop synchronizer has a phase comparator based on analog components such as the multiplier. The previous block generates the pulse D (Fig.2).    Fig.2 Analog closed loop symbol synchronizer (DPLL-ana)  This DPLL inputs (main input and VCO output feedback) are both analog. Fig.3 shows the operation mode waveforms of the analog closed loop data synchronizer.    Fig.3 Waveforms of the analog closed loop synchronizer  At the equilibrium point, the positive area is equal to the negative one, so the error pulse average Pe tends to zero.  B. Hybrid closed loop data synchronizer  The hybrid closed loop synchronizer has a phase comparator based on hybrid components such as the real switch. The previous block generates the pulse D (Fig.4).   Data Phase Synchronizers of Closed Loop Antonio D. Reis, Jose F. Rocha, Atilio S. Gameiro and Jose P. Carvalho Proceedings of the World Congress on Engineering 2018 Vol I WCE 2018, July 4-6, 2018, London, U.K.ISBN: 978-988-14047-9-4 ISSN: 2078-0958 (Print); ISSN: 2078-0966 (Online)WCE 2018    Fig.4 Hybrid closed loop symbol synchronizer (DPLL-hib)  This DPLL main input is digital but the VCO output feedback continues to be analog. Fig.5 shows the operation mode waveforms of the hybrid closed loop data synchronizer.     Fig.5 Waveforms of the hybrid closed loop synchronizer  At the equilibrium point, the positive area is equal to the negative one, so the error pulse average Pe tends to zero.  C. Combinational closed loop data  synchronizer  The combinational closed loop synchronizer has a phase comparator based on combinational components such as the AND gate. The previous bloc generates the pulse D (Fig.6).    Fig.6 Combinational closed loop data synchronizer (DPLL-cmb)  This DPLL inputs (main input and VCO output feedback) are both digital, but the output is only function of the inputs. Fig.7 shows the operation mode waveforms of the combinational closed loop data synchronizer.    Fig.7 Waveforms of the combinational closed loop synchronizer  At the equilibrium point, the positive area is equal to the negative one, so the error pulse average Pe tends to zero.   D. Sequential closed loop data synchronizer  The sequential closed loop synchronizer has a phase comparator based on sequential components such as the flip flop. It don’t needs the previous pulse (Fig.8).    Fig.8 Sequential closed loop data synchronizer (DPLL-seq)  This DPLL inputs (main input and VCO output feedback) are both digital, but the output is function of the inputs and also of the state. Fig.9 shows the operation mode waveforms of the sequential closed loop data synchronizer.    Fig.9 Waveforms of the sequential closed loop synchronizer  In synchronism, the error pulse Pe diminishes its area, tends to zero and disappear at the equilibrium point.  III. PROJECT, TESTS AND RESULTS We present the project, the tests and the results of the referred  synchronizers [5].  A. Project  We project all the synchronizers with the same loop gain conditions to have guaranteed results. The loop gain is Kl = Ka.Kf.Ko, where Kf and Ko are fixed. The Ka is the variable parameter that controls the loop characteristics. To facilitate the analysis, we use normalized values for the bit rate tx= 1baud, clock frequency fCK=1Hz, extern noise bandwidth Bn=5Hz and loop noise bandwidth Bl=0.02Hz. We apply a power signal Ps= A2ef with power noise Pn= No.Bn= 2σn2.∆τ.Bn, where σn is the noise standard deviation and ∆τ =1/fSampling is the sampling period. Then, the relation between SNR and noise variance σn2 is SNR= Ps/Pn= A2ef/(No.Bn)= 0.52/(2σn2*10-3*5)= 25/σn2 (1) Now, for each synchronizer, we must measure the output jitter UIRMS versus the input SNR    - 1st order loop:  The loop filter F(s)=1 has cutoff fc=0.5Hz, which is 25 times greater than Bl= 0.02Hz, eliminates the high frequency but maintains the loop characteristics.   Proceedings of the World Congress on Engineering 2018 Vol I WCE 2018, July 4-6, 2018, London, U.K.ISBN: 978-988-14047-9-4 ISSN: 2078-0958 (Print); ISSN: 2078-0966 (Online)WCE 2018  The transfer function is  H(s)=G(s)1 G(s)+=+=+KdKoF ss KdKoF sKdKos KdKo( )( )                   (2)  the loop noise bandwidth is  Bl = KdKoKaKfKo4 4=  = 0.02Hz                                   (3)  So, with (Km=1, A=1/2, Ba=1/2, Bh=0.45, Ko=2π) and loop bandwidth Bl=0.02, we obtain respectively the Ka, for analog, hybrid, combinational and sequential synchronizers:  Bl=(Ka.Kf.Ko)/4 = (Ka.Km.A.Ba .Ko)/4 -> Kaa=0.08*2/π   (4) Bl=(Ka.Kf.Ko)/4 = (Ka.Km.A.Bh.Ko)/4 -> Kah=0.08*2.2/π  (5) Bl=(Ka.Kf.Ko)/4 = (Ka*1/π*2π)/4 -> Kac=0.04             (6) Bl=(Ka.Kf.Ko)/4 = (Ka*1/2π*2π)/4 -> Kas=0.08             (7)  For the analog PLL, the jitter is    σφ2=Bl.No/Aef2=0.02*10-3*2σn2/0.52=16*10-5.σn2         (8)  For the others PLLs, the jitter formula is more complicated.  - 2nd order loop:  It is not used here, but provides similar results.  B. Tests  Following Fig.10 shows the setup that was used to test the various  synchronizers.    Fig.10 Block diagram of the test setup  The receiver recovered clock with jitter is compared with the emitter original clock without jitter, the difference is the jitter of the received clock.  C. Jitter measurer (Meter)  The jitter measurer (Meter) consists of a RS flip flop, which detects the random variable phase of the recovered clock (CKR), relatively to the fixed phase of the emitter clock (CKE). This relative random phase variation is the recovered clock jitter (Fig.11).    Fig.11 The jitter measurer (Meter)  The other blocks convert this random phase variation into a random amplitude variation, which is the jitter histogram. Fig.12 illustrates the operation of the jitter measurer.     Fig.12 Waveforms at the jitter measurer  Then, the jitter histogram is sampled and processed by an appropriate program, providing the RMS jitter and the peak to peak jitter.  D. Results  We will present the results (output jitter UIRMS versus input SNR) for the four closed loop data synchronizers. Fig.13 shows the jitter - SNR curves of the four synchronizers: analog data synchronizer (DPLL-ana), hybrid data synchronizer (DPLL-hib), combinational data synchronizer (DPLL-cmb) and sequential data synchronizer (DPLL-seq).   Fig.13 Jitter-SNR curves of  the four synchronizers(ana,hib,cmb,seq)  We see, that generally the output jitter UIRMS diminishes almost exponentially with the input SNR increasing. For high SNR, the synchronizers with input limiter (DPLL-hib, DPLL-cmb, DPLL-seq) are similar and have a slightly advantage over the synchronizer without input limiter (DPLL-ana). However, for low SNR, the synchronizers without intern memory (DPLL-ana, DPLL-hib, DPLL-cmb) have a slightly advantage over the synchronizer with intern memory (DPLL-seq).  IV. CONCLUSIONS We studied four data phase synchronizers of closed loop, or data phase lock loop namely the analog (DPLL-ana), the hybrid (DPLL-hib), the combinational (DPLL-cmb) and the sequential (DPLL-seq). Then, we tested their output jitter UIRMS versus input SNR. We saw that, generally, the output jitter UIRMS diminishes almost exponentially with the input SNR increasing. We verified that, for high SNR, the synchronizers with input limiter (DPLL-hib, DPLL-cmb, DPLL-seq), have a slightly advantage over the others without input limiter (DPLL-ana). This is comprehensible since the input limiter is a digital components with noise margin what ignores low noise spikes.  Proceedings of the World Congress on Engineering 2018 Vol I WCE 2018, July 4-6, 2018, London, U.K.ISBN: 978-988-14047-9-4 ISSN: 2078-0958 (Print); ISSN: 2078-0966 (Online)WCE 2018 However, for low SNR, the synchronizers with intern memory (DPLL-seq) have a slightly disadvantage relatively to the others synchronizers without intern memory (DPLL-ana, DPLL-hib, DPLL-cmb). This is comprehensible since the intern memory provokes random switching between the memory states, what increments the jitter. This disadvantage can be minimized with a prefilter. Anyway, the intern memory provides important project potentialities. In the future, we are planning to extend this study to other new synchronizers.  ACKNOWLEDGMENTS  The authors are grateful to the program FCT (Foundation for sCience and Technology).  REFERENCES [1] Jean C. Imbeaux, “performance of the delay-line multiplier circuit for clock and carrier synchronization”, IEEE Jou. on Selected Areas in Communications p.82 Jan. 1983. [2] Werner Rosenkranz, “Phase Locked Loops with limiter phase detectors in the presence of noise”, IEEE Trans. on Communications com-30 Nº10 pp.2297-2304. Oct 1982. [3] Hans H. Witte, “A Simple Clock Extraction Circuit Using a Self Sustaining Monostable Multivibrat. Output Signal”, Electronics Letters, Vol.19, Is.21, pp.897-898, Oct 1983. [4] Charles R. Hogge, “A Self Correcting Clock Recovery Circuit”, IEEE Tran. Electron Devices p.2704 Dec 1985. [5] Antonio D. Reis, Jose F. Rocha, Atilio S. Gameiro, Jose P. Carvalho “A New Technique to Measure the Jitter”, Proc. III Conf. Telecommunications pp.64-67 FFoz-PT 23-24 Apr 2001. [6] Marvin K. Simon, William C. Lindsey, “Tracking Performance of Symbol Synchronizers for Manchester Coded Data”, IEEE Transactions on Communications Vol. com-2.5 Nº4, pp.393-408, April 1977. [7] J. Carruthers, D. Falconer, H. Sandler, L. Strawczynski, “Bit Synchronization in the Presence of Co-Channel Interference”, Proc. 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Carvalho “Carrier Phase Lock Loop and Bit Phase Lock Loop”, Proc. IX Symposium on Enabling Optical Network and Sensors (SEONs) p.CD-Edited, Aveiro-PT 1-1 July 2011. [13] A. D. Reis, J. F. Rocha, A. S. Gameiro, J. P. Carvalho “Optical Digital Communication Systems and Synchronism”, Proc. 7th UBI International Conference on Engeneering (for Economic Development) - ICEUBI 2013, pp. CT8-11.7, Covilhã-PT 27-29 November 2013.     [14] A. D. Reis, J. F. Rocha, A. S. Gameiro, J. P. Carvalho, “Synchronizers Operating Synchronously and Asynchronously by All Transitions at Rate”, Proc. SEONs 2016 - XIII Symposium on Enabling Optic Network and Sensors, PP. 31-34, Covilha, 8 July 2016. [15] A. D. Reis, J. F. Rocha, A. S. Gameiro, J. P. Carvalho, “Asynchronous Sequential Symbol Synchronizers based on Pulse Comparison by Positive Transitions at Quarter Bit Rate”, Proc. World Congress on Engineering 2016, ‘WCE 2016’, pp.257-261, London-UK, 29 June - 1 July 2016.   Proceedings of the World Congress on Engineering 2018 Vol I WCE 2018, July 4-6, 2018, London, U.K.ISBN: 978-988-14047-9-4 ISSN: 2078-0958 (Print); ISSN: 2078-0966 (Online)WCE 2018

Data phase synchronizers of closed loop

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Data phase synchronizers of closed loop

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