This work studies the effects of the prefilter bandwidth on the carrier phase synchronizers.
We apply three different prefilter bandwidth namely B1=¥ (infinite), B2=2.tx and B3=1.tx, where tx is the transmissionrate.
We consider also four carrier wave phase synchronizers namely the analog (ana), the hybrid (hib), the combinational (cmb) and the sequential (seq).
The objective is to study the prefilter bandwidth with the four carrier synchronizers and to evaluate their output jitter UIRMS (Unit Interval Root Mean Square) versus input SNR (Signal to Noise Ratio).University of Beira Interiorinfo:eu-repo/semantics/publishedVersio

Carvalho, José Pacheco de

Gameiro, Atilio

Reis, António

Rocha, José Ferreira da

English

UBibliorum repositorio digital da ubi

   Abstract - This work studies the effects of the prefilter bandwidth on the carrier phase synchronizers. We apply three different  prefilter bandwidth namely B1=¥ ( infinite), B2=2.tx and  B3=1.tx, where tx is the transmission rate. We consider also four carrier wave phase synchronizers namely the analog (ana), the hybrid (hib), the combinational (cmb) and the sequential (seq). The objective is to study the prefilter bandwidth with the four carrier synchronizers and to evaluate their output jitter UIRMS (Unit Interval Root Mean Square) versus input SNR (Signal to Noise Ratio).  Index Terms—Prefilter, Digital Communication Systems  I. INTRODUCTION This work studies the prefilter bandwidth effects on the jitter - noise behavior of four carrier synchronizer types. The Butterworth prefilter, applied before the synchronizer, varies their bandwidth between three values: first B1=∞, next B2=2.tx and after B3=1.tx, tx is the transmission rate value. The carrier phase synchronizers has four types namely the analog (ana), the hybrid  (hib), the combinational (cmb) and the sequential (seq) [1, 2, 3, 4, 5, 6, 7, 8]. The difference between the four synchronizers is only in the phase comparator, hence, the other blocks are equals. The carrier synchronizer is able to synchronize its output VCO (Voltage Controlled Oscillator) directly with the main input carrier. The VCO output carrier is an improved quality version of the input carrier [9, 10, 11, 12, 13, 14]. Fig.1 shows the prefilter followed of the synchronizer.   Fig.1 Prefilter with the carrier synchronizer  PF(s) is the prefilter (low pass). The synchronizer has various blocks namely, Kf is the phase comparator gain, (Fs) is the loop filter, Ko is the VCO gain and Ka is the loop gain factor, that controls the root locus and loop characteristics. In prior and actual art-state was developed various synchronizers, now is necessary to know their performance.  Manuscript received August 18, 2017; Supports from UBI (University of Beira Interior) and FCT (Foundation for sCience and Technology). A. D. Reis is with the University of Beira Interior Covilha and Goup of A. P. and Telecommunications, Portugal (e-mail: adreis@ ubi.pt). J. F. Rocha is with the University of Aveiro and Institute of Telecommunications, Portugal (e-mail: frocha@ ua.pt). A. S. Gameiro is with the University of Aveiro and Institute of Telecommunications, Portugal (e-mail: amg@ ua.pt). J. P. Carvalho is with the University of Beira Interior Covilha and Group of A. P. and Telecom., Portugal (e-mail: pacheco@ ubi.pt).  The motivation of this work is to create new synchronizers and to see the prefilter effects. This contribution increases the know how about the prefilter effects in synchronizers.   Following, we present the prefilter with their three different bandwidths (B1=∞, B2=2.tx, B3=1.tx). Next, we present the four carrier synchronizers namely the analog (ana), hybrid (hib), combinational (cmb) and sequential (seq). After, we present the design and tests. Then, we present the results. Finally, we present the conclusions.  II. PREFILTER BANDWIDTH EFFECTS The prefilter applied before the synchronizer, filters the noise but disturbs slightly the signal. The prefilter bandwidth is switched between three values (B1=∞, B2=2.tx, B3=1.tx). Fig.2 shows the prefilter with their three bandwidths.   Fig.2 Three bandwidths prefilter: B1=∞ (a), B2=2.tx (b), B3=1.tx (c)  a) First (Fig.2a), the prefilter has a bandwidth equal to infinite (B1= ∞). b) Second (Fig.2b), the prefilter has a bandwidth equal two times the transmission rate (B2 = 2.tx). c) Third (Fig.2c), the prefilter has a bandwidth equal to the transmission rate (B3 = 1.tx). We will evaluate the three bandwidth effects (B1, B2, B3) on the jitter-SNR curves of the four carrier synchronizers.  III. FOUR CARRIER PLLs We present the four carrier phase synchronizers, or carrier phase lock loop (CPLL), namely the analog, the hybrid, the combinational and the sequential. The difference between them is only in the phase comparator [2].  A. Analog carrier PLL  The analog carrier PLL has a phase comparator based on the ideal multiplier (analog component) (Fig.3).    Fig.3 Analog carrier PLL (PLL-ana)  The phase comparator inputs (main input and VCO output feedback) are both analog.  Prefilter Bandwidth Effects in Carrier Phase Synchronizers Antonio D. Reis, Jose F. Rocha, Atilio S. Gameiro and Jose P. Carvalho Proceedings of the World Congress on Engineering 2018 Vol I WCE 2018, July 4-6, 2018, London, U.K.ISBN: 978-988-14047-9-4 ISSN: 2078-0958 (Print); ISSN: 2078-0966 (Online)WCE 2018 B. Hybrid  carrier PLL  The hybrid carrier PLL has a phase comparator based on the switch or real multiplier (hybrid component) (Fig.4).    Fig.4 Hybrid carrier PLL (PLL-hib)  The phase comparator main input is now digital, but the input coming from the VCO output feedback is still analog.  C. Combinational carrier PLL  The combinational carrier PLL has a phase comparator based on the exor gate (combinational component) (Fig.5).    Fig.5 Combinational carrier PLL (PLL-cmb)  The phase comparator inputs (main input and VCO output feedback) are both digital. The output is only function of the inputs.  D. Sequential carrier  PLL  The sequential carrier PLL has a phase comparator based on the flip flop (sequential component) (Fig.6).    Fig.6 Sequential carrier PLL (PLL-seq)  The phase comparator inputs (main input and VCO output feedback) are both digital. The output is function of the inputs and phase comparator state (circuit with memory).  IV. DESIGN, TESTS AND RESULTS We will present the design, the tests and the results of the referred  synchronizers [5].  A. Design  To get guaranteed results, it is necessary to dimension all the synchronizers with equal conditions. Then it is necessary to design all the loops with identical linearized transfer functions. The general loop gain is Kl=Kd.Ko=Ka.Kf.Ko where Kf is the phase comparator gain, Ko is the VCO gain and Ka is amplification factor that controls the root locus that provides the desired characteristics. For analysis facilities, we use a normalized transmission rate tx=1baud, what implies also normalized values for the others dependent parameters. So, the normalized clock frequency is fCK=1Hz. We choose a normalized external noise bandwidth Bn = 5Hz and a normalized loop noise bandwidth Bl = 0.02Hz. Later, we can disnormalize these values to the appropriated transmission rate tx. Now, we will apply a signal with noise ratio SNR given by the signal amplitude Aef, noise spectral density No and external noise bandwidth Bn, so the SNR = A2ef/(No.Bn). But, No can be related with the noise variance σn and inverse sampling ∆τ=1/Samp, then No=2σn2.∆τ, so:  SNR=A2ef/(2σn2.∆τ.Bn) = 0.52/(2σn2*10-3*5)= 25/σn2 (1) After, we observe the output jitter UI as function of the input signal with noise SNR. The dimension of the loops is  - 1st order loop: The loop filter F(s)=1 with cutoff frequency 0.5Hz (Bp=0.5 Hz is 25 times bigger than Bl=0.02Hz) eliminates only the high frequency, but maintain the loop characteristics. The transfer function is   H(s)=G(s)1 G(s)+=+=+KdKoF ss KdKoF sKdKos KdKo( )( )                 (2)  the loop noise bandwidth is  Bl = KdKoKaKfKo4 4=  = 0.02Hz                                (3)  Then, for the analog synchronizers, the loop bandwidth is Bl=0.02=(Ka.Kf.Ko)/4 with (Km=1, A=1/2, B=1/2; Ko=2π) (Ka.Km.A.B.Ko)/4 = 0.02 -> Kaa=0.08*2/π                       (4)  For the hybrid synchronizers, the loop bandwidth is                                                   Bl=0.02=(Ka.Kf.Ko)/4 with (Km=1, A=1/2, B=0.45; Ko=2π) (Ka.Km.A.B.Ko)/4 = 0.02 -> Kah=0.08*2.2/π                     (5)  For the combinational synchronizers, the loop bandwidth is Bl=0.02=(Ka.Kf.Ko)/4     with     (Kf=1/π; Ko=2π) (Ka*1/π*2π)/4 = 0.02 -> Kac=0.04                                 (6)  For the sequential synchronizers, the loop bandwidth is                                                Bl=0.02=(Ka.Kf.Ko)/4     with     (Kf=1/2π; Ko=2π) (Ka*1/2π*2π)/4 =0.02 -> Kas=0.08                                (7)  The jitter depends on the RMS signal Aef, on the power spectral density No and on the loop noise bandwidth Bl.  For the analog PLL the jitter is σφ2=Bl.No/Aef2    σφ2 =Bl.2.σn2.∆τ/Aef2=0.02*10-3*2σn2/0.52=16*10-5.σn2      (8) For the others PLLs the jitter formula is more complicated.  - 2nd order loop: The second order loop is not shown here, but the results are identical to the ones obtained above for the first order loop.  B. Tests  The following figure (Fig.7) shows the setup that was used to test the various  synchronizers.    Fig.7 Block diagram of the test setup  The receiver recovered clock with jitter is compared with the emitter original clock without jitter, the difference is the jitter of the received clock. Proceedings of the World Congress on Engineering 2018 Vol I WCE 2018, July 4-6, 2018, London, U.K.ISBN: 978-988-14047-9-4 ISSN: 2078-0958 (Print); ISSN: 2078-0966 (Online)WCE 2018 C. Jitter measurer (Meter)  The jitter measurer (Meter) consists of a RS flip flop, which detects the random variable phase of the recovered clock (CKR), relatively to the fixed phase of the emitter clock (CKE). This relative random phase variation is the recovered clock jitter (Fig.8).    Fig.8 The jitter measurer (Meter)  The other blocks convert this random phase variation into a random amplitude variation, which is the jitter histogram. Fig.9 shows the operation mode of the jitter measurer.     Fig.9 Waveforms at the jitter measurer  Then, the jitter histogram is sampled and processed by an appropriate program, providing the UIRMS jitter and the peak to peak jitter UIPP.  D. Results  We present the results (output jitter UIRMS - input SNR) for the prefilter with the four carrier PLLs. Fig.10 shows the jitter-SNR curves of the prefilter bandwidth B1= ∞, with the four carrier PLLs: analog (PLL-ana), hybrid (PLL-hib), combinational (PLL-cmb) and sequential (PLL-seq).  Fig.10 Jitter-SNR curves of  the four P1+PLLs  (P-a, P-h, P-c, P-s)  We observe that, generally, the output jitter diminishes almost exponentially with the input SNR increasing. For the prefilter with B1= ∞, we verify that, for high SNR, the carrier PLL without input limiter (PLL-ana) is disadvantageous over the others with input limiter (PLL-hib, PLL-cmb, PLL-seq). However, for low SNR, the carrier PLL with phase comparator with intern memory (PLL-seq) is slightly disadvantageous over the others with phase comparator without intern memory (PLL-ana, PLL-hib, PLL -cmb). This disadvantage can be minimized with a prefilter. Fig.11 shows the jitter-SNR curves of the prefilter bandwidth B2= 2.tx, with the four carrier PLLs: analog (PLL-ana), hybrid (PLL-hib), combinational (PLL-cmb) and sequential (PLL-seq).  Fig.11 Jitter-SNR curves of  the four P2+PLLs  (P-a, P-h, P-c, P-s)  We verify that, the prefilter bandwidth B2 = 2.tx becomes the four synchronizer jitter-SNR curves more similar one another. Fig.12 shows the jitter-SNR curves of the prefilter bandwidth B2= 2.tx, with the four carrier PLLs: analog (PLL-ana), hybrid (PLL-hib), combinational (PLL-cmb) and sequential (PLL-seq).  Fig.12 Jitter-SNR curves of  the four P3+PLLs  (P-a, P-h, P-c, P-s)  We note that, the prefilter bandwodth B3 = 1.tx becomes the four synchronizer jitter-SNR curves still more similar between them.  V. CONCLUSIONS AND FUTURE WORK We studied the prefilter of three bandwidths (B1= ∞, B2=2.tx, B3=1.tx) applied before the four carrier synchronizers (PLL-ana, PLL-hib, PLL-cmb, PLL-seq). We noted that, in general, the output jitter decreases almost exponentially with the input SNR increasing. For the prefilter B1=∞ (greater), we verified that, for high SNR, the carrier PLL without input limiter (PLL-ana) is disadvantageous in relation to the others with input limiter (PLL-hib, PLL-cmb, PLL-seq). This is comprehensible since the digital limiter noise margin ignores low noise spikes. However, for low SNR, the carrier PLL with phase comparator with intern memory (PLL-seq) is disadvantageous over the others with phase comparator without intern memory (PLL-ana, PLL-hib, PLL-cmb). This is comprehensible since the high noise spikes provokes commutations to the error states that contributes to the jitter. Anyway, this disadvantage can be minimized with a prefilter. For the prefilter B2=2.tx (medium), the four synchronizer jitter - SNR curves becomes more similar one another. For the prefilter B3=1.tx (lesser), the four synchronizer jitter - SNR curves becomes still more similar to each other. Then, the prefilter tends to approximate the synchronizers jitter-SNR curves. So, the prefilter is prejudicial for high SNR and beneficial for low SNR. In the future, we are planning to study the effects of the prefilter in other synchronizers types.  Proceedings of the World Congress on Engineering 2018 Vol I WCE 2018, July 4-6, 2018, London, U.K.ISBN: 978-988-14047-9-4 ISSN: 2078-0958 (Print); ISSN: 2078-0966 (Online)WCE 2018 ACKNOWLEDGMENTS  The authors are grateful to the program FCT (Foundation for sCience and Technology).  REFERENCES [1] J. C. Imbeaux, “performance of the delay-line multiplier circuit for clock and carrier synchronization”, IEEE Jou. on Selected Areas in Communications p.82 Jan. 1983. [2] Werner Rosenkranz, “Phase Locked Loops with limiter phase detectors in the presence of noise”, IEEE Trans. on Communications com-30 Nº10 pp.2297-2304. Oct 1982. [3] H. H. Witte, “A Simple Clock Extraction Circuit Using a Self Sustaining Monostable Multivibrat. Output Signal”, Electronics Letters, Vol.19, Is.21, pp.897-898, Oct 1983. [4] Charles R. Hogge, “A Self Correcting Clock Recovery Circuit”, IEEE Tran. Electron Devices p.2704 Dec 1985. [5] A. D. Reis, J. F. Rocha, A. S. Gameiro, J. P. Carvalho “A New Technique to Measure the Jitter”, Proc. III Conf. on Telecommunications pp.64-67 FFoz-PT 23-24 Apr 2001. [6] Marvin K. Simon, William C. Lindsey, “Tracking Performance of Symbol Synchronizers for Manchester Coded Data”, IEEE Transactions on Communications Vol. com-2.5 Nº4, pp.393-408, April 1977. [7] J. Carruthers, D. Falconer, H. Sandler, L. Strawczynski, “Bit Synchronization in the Presence of Co-Channel Interference”, Proc. Conf. on Electrical and Computer Engineering pp.4.1.1-4.1.7, Ottawa-CA 3-6 Sep. 1990. [8] Johannes Huber, W. Liu “Data-Aided Synchronization of Coherent CPM-Receivers” IEEE Transactions on Communications Vol.40 Nº1, pp.178-189, Jan. 1992. [9] Antonio D’Amico, A. D’Andrea, Reggianni, “Efficient Non-Data-Aided Carrier and Clock Recovery for Satellite DVB at Very Low SNR”, IEEE Jou. on Sattelite Areas in Comm. Vol.19 Nº12 pp.2320-2330, Dec. 2001. [10] Rostislav Dobkin, Ran Ginosar, Christos P. Sotiriou “Data Synchronization Issues in GALS SoCs”, Proc. 10th International Symposium on Asynchronous Circuits and Systems, pp.CD-Ed., Crete-Greece 19-23 Apr. 2004. [11] N. Noels, H. Steendam, M. Moeneclaey, “Effectiveness Study of Code-Aided and Non-Code-Aided ML-Based Feedback Phase Synchronizers”, Proc. IEEE Int Conf. on Comm.(ICC’06) pp.2946-2951, Ist.-TK, 11-15 Jun 2006. [12] A. D. Reis, J. F. Rocha, A. S. Gameiro, J. P. Carvalho “Effects of the Prefilter Type on Digital Symbol Synchronizers”, Proc. VII Symposium on Enabling Optical Network and Sensors (SEONs 2009) pp.35-36, Lisboa (Amadora)-PT 26-26 June 2009. [13] A. D. Reis, J. F. Rocha, A. S. Gameiro, J. P. Carvalho, “Synchronizers Operating Synchronously and Asynchronously by All Transitions at Rate”, Proc. SEONs 2016 - XIII Symposium on Enabling Optic Network and Sensors, PP. 31-34, Covilha, 8 July 2016. [14] A. D. Reis, J. F. Rocha, A. S. Gameiro, J. P. Carvalho, “Asynchronous Sequential Symbol Synchronizers based on Pulse Comparison by Positive Transitions at Quarter Bit Rate”, Proc. World Congress on Engineering 2016, ‘WCE 2016’, pp.257-261, London-UK, 29 June - 1 July 2016.    Proceedings of the World Congress on Engineering 2018 Vol I WCE 2018, July 4-6, 2018, London, U.K.ISBN: 978-988-14047-9-4 ISSN: 2078-0958 (Print); ISSN: 2078-0966 (Online)WCE 2018

Prefilter bandwidth effects in carrier phase synchronizers

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Prefilter bandwidth effects in carrier phase synchronizers

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